High-Density Memristor-CMOS Ternary Logic Family

Abstract

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Logic Implementation Based on Double Memristors

“…(a), the resistances of the memristors and the resistor are expressed as conductance. According to Kirchhoff's voltage law, we could deduce (1) and (2). And these equations could be established for any current direction.…”

“…However, memristor-based logic operation is one of the potential approaches to overcome these challenges and realize the in-memory computing without separation between storage and computation [1]. Memristor-based logic has many challenges such as resistive dissipation, slow switching speed of memristors, but its main advantage make up for the above deficiencies that increasing chip density by integrating RRAM in the BEOL [2].…”

FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

“…Besides, because memristors are compatible with the CMOS technology, so the memristor based compound logic circuits such as NAND gate and NOR gate can be obtained by using CMOS NOT gates, and then combined logic circuits, such as adders, decoders and encoders can be realized too. In order to realize the memristor based AND gate, the positive terminals of the two memristors need to be connected and led out as the output terminals of the AND gates, and the two negative ends are, respectively, used as the input signal terminals [19], as shown in Figure 4a. When both input terminals are at a high level, the output is also at a high level; when both input terminals are low, the output is also low.…”

“…Because of the symmetry of the circuit, the same result is obtained when the input level is switched. In order to realize the memristor based AND gate, the positive terminals of the two memristors need to be connected and led out as the output terminals of the AND gates, and the two negative ends are, respectively, used as the input signal terminals [19], as shown in Figure 4a. When both input terminals are at a high level, the output is also at a high level; when both input terminals are low, the output is also low.…”

“…This kind of circuit has fewer devices, less circuit area and power consumption, and also the data density is improved. [16][17][18][19]. In recent years, many digital logic circuits based on memristors and CMOS transistors have been proposed, such as adders [20,21], multipliers [22][23][24], counters [25], decoders [26] and maximum and minimum circuits [14], etc., which play an important role in digital systems.…”