2008
DOI: 10.1063/1.2840188
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High density platinum nanocrystals for non-volatile memory applications

Abstract: High density self-assembled platinum nanodots are elaborated using a radio frequence sputtering technique and embedded in memory structures. Electronic microscopy methods are used to characterize the morphology. Scanning electron microscopy and scanning transmission electron microscopy observations allow quantification of the density (>3×1012cm−2) and size (2–3nm) of the nanocrystals, whereas their crystallinity is investigated using high-resolution transmission electron microscopy. Then, capacitance-vo… Show more

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Cited by 63 publications
(42 citation statements)
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“…4,5 While the display of appealing physical and chemical properties originally triggered the investigation of QDs, it is now equally important for the development of several QDs-based nanoelectronic, optoelectronic, and nanolithography applications to acquire the capability of fast, parallel fabrication of high-density arrays of laterally ordered nanoislands. 6,7 This architecture is likely to result from bottom-up, self-assembly processes in which nanodots ordering is driven from internal fluxes and forces, like the stress field occurring at Si-Ge interface during Ge/ Si heteroepitaxy, perhaps coupled to some form of nanopatterning. [8][9][10] Therefore, the acquisition of an ultimate control and understanding of in-plane interactions of QDs at surfaces is an urgent need for nanotechnology, and the detection of any degree of self-ordering among nanostructures, which may well elude visual inspection, is of great help in this undertaking.…”
mentioning
confidence: 99%
“…4,5 While the display of appealing physical and chemical properties originally triggered the investigation of QDs, it is now equally important for the development of several QDs-based nanoelectronic, optoelectronic, and nanolithography applications to acquire the capability of fast, parallel fabrication of high-density arrays of laterally ordered nanoislands. 6,7 This architecture is likely to result from bottom-up, self-assembly processes in which nanodots ordering is driven from internal fluxes and forces, like the stress field occurring at Si-Ge interface during Ge/ Si heteroepitaxy, perhaps coupled to some form of nanopatterning. [8][9][10] Therefore, the acquisition of an ultimate control and understanding of in-plane interactions of QDs at surfaces is an urgent need for nanotechnology, and the detection of any degree of self-ordering among nanostructures, which may well elude visual inspection, is of great help in this undertaking.…”
mentioning
confidence: 99%
“…Thus, the V FB shift of the active device is attributed to electron charging in Pt NP or at the interface between NP and Al 2 O 3 , not from the defects in Al 2 O 3 [13]. Counterclockwise hysteresis loops were observed, indicating electron injection from substrate to Pt NPs under positive voltage for the programming and hole injection under negative voltage for erasing by Fowler-Nordheim (F-N) tunneling [7]. It was also shown that V FB shift under different sweeping voltages gradually increased with a uniform increase of F-N injection and finally saturated over a certain value within the measurement range.…”
Section: Device Fabricationmentioning
confidence: 94%
“…Specific to Pt NPs, two examples of NP formation processes include thermal dewetting technique [7], [8] and electron beam evaporation [9]. The first technique does not satisfy a low thermal budget and the particle distributions are broad, and the second technique shows inability to control uniform and spherically shaped NPs smaller than 5 nm.…”
Section: Introductionmentioning
confidence: 99%
“…Then, a lot of attention has been put on Ge-NCs [14][15][16], for which very good data retention has been obtained for holes because of the higher valence-band offset. More recently, metallic dots embedded in SiO 2 have been proposed as a way of obtaining a higher conduction-band offset [17][18][19]. Despite attractive results, this latter approach suffers from limitations in the thermal budget applied after dot fabrication, which may induce metal and oxide reactions or/and metal diffusion toward the silicon substrate and thereby, degrade the device performance.…”
Section: Introductionmentioning
confidence: 97%