High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

Abstract

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

A Hardware Security Protection Method for Conditional Branches of Embedded Systems

“…However, they used a simple hardware random number generator, which makes it difficult to adequately secure the ciphertext. Researchers in our lab proposed an efficient cryptographic accelerator that could protect dynamic data security of embedded systems [25]. After that, they proposed two post-quantum cryptographic algorithms that could improve higher levels of cryptographic protection for critical data.…”

“…However, although these algorithms have extremely high security and can defend against quantum attacks, they have high resource overhead, long encryption and decryption times, and are not suitable for branching information. Our team has also designed the hardware accelerator based on traditional cryptographic algorithms such as AES-GCM [25]. However, this module is more suitable for confidentiality protection applications with large amounts of data and has high resource overhead.…”

A Dynamic Multitarget Detection Algorithm in front of Vehicle Based on Embedded System and Internet of Things

“…e two-stage detection algorithm concept is as follows: first, employ algorithm for location information [14]; secondly, produce classification for category information. According to the proposed model, the focus is on real-time detection [15]. e single-stage detection method introduces a novel concept: the dynamic multitarget image in front of the vehicle is transformed into network output [16] by returning the category of bounding box position in the output layer [17] and transforming multitarget detection problem to regression problem by improving the detection speed [18][19][20].…”

A Hardware Security Protection Method for Conditional Branches of Embedded Systems

“…However, some references pointed out that PUF circuits had difficulty resisting machine learning (ML) attacks [ 21 ]. Moreover, we attempted to use the higher security cryptographic algorithms [ 11 , 12 , 22 ], but the performance and resource overhead of these cryptographic circuits were significant, which made it difficult to achieve confidentiality protection for branch information in lightweight embedded processors.…”