High efficient motion estimation architecture with integrated Motion Compensation and FME support

Abstract

This paper presents an efficient architecture for Motion Estimation (ME) based on the Diamond Search (DS) Algorithm. This architecture also includes the Motion Compensation (MC) for luminance samples, reusing internal ME results and avoiding the additional external memory accesses for the MC operation. The proposed architecture also generates inputs for a Fractional Motion Estimation (FME) for quarter sample precision, as proposed by the H.264/AVC standard. The main goal of this work is to design a low cost ME architecture for the DS algorithm with reduced number of external memory accesses and ready to be integrated with a fractional interpolator. The designed architecture was synthesized to Altera Stratix 4 family of FPGAs and in the worst case scenario, this architecture is able to process Full HD (1080p) videos in real time.

Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

“…Owing to that recourse utilisation measured by look‐up tables (LUTs) or gate count are different and cannot be used as a figure of merit. Implementations presented in [3, 6, 8, 10] need more than nine clock cycles for SAD computation of single macroblock while the same operation can be performed in single clock cycle by Shah and Dalal [1] and the proposed architecture. Owing to dissimilar heuristic number of the clock cycle in average case for MV computation is having a larger range.…”

“…With 128 bit data bus width, Vanne's architecture uses 390 clock cycles in average case for HEXBS search pattern with fixed 16 × 16 block size [6]. Porto's [3] and Sanchez's [10] architecture use 130 clock cycles in average case for 4:1 subsampled DS search pattern with fixed 8 × 8 block size. Single memory system architecture [1] uses 89 clock cycles in average case for HEDDS search pattern with fixed 8 × 8 block size for HD sequences.…”

“…Various architectures use dissimilar width of data bus, hence can read and process distinctive number of pixels. Owing to 128 bit data bus width in [4, 9, 10], they can read 16 keel pixel together from search area while due to 32 and 64 bit data bus, implementations presented in [5, 7], can read 4 and 8 keel pixel together. As per Table 2, all existing architectures are using different schemes for multi‐operand addition and process different numbers of pixels in multiple PEs with or without pipeline for SAD computation.…”

“…As per review of literature, for accessing CMBs, architecture presented in [1, 4, 5, 7, 9, 10] are using single memory system while architecture presented in [6] uses parallel memory system. In [6], just block format is used for reading pixels; however, according to [11, 12], parallel memory system can help in accessing pixels in various formats from arbitrary locations.…”

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

“…The DMPDS architecture is formed by five DS cores and some additional logic to dynamically control the d parameter, to define which is the best vector among the five cores and to group these DS cores. Figure 8 presents the block diagram of the DS architecture, which is strongly based on the DS architecture presented in [13] for this module. To start the ME process, it is necessary to fill the reference memory and the current memory.…”