Bias stress effects in n-channel organic field-effect transistors (OFETs) are investigated using PDIF-CN 2 single-crystal devices with Cytop gate dielectric, both under vacuum and in ambient. We find that the amount of bias stress is very small as compared to all (p-channel) OFETs reported in the literature. Stressing the PDIF-CN 2 devices by applying 80 V to the gate for up to a week results in a decrease of the source drain current of only ~1% under vacuum and ~10% in air. This remarkable stability of the devices leads to characteristic time constants, extracted by fitting the data with a stretched exponential -that are τ ~ 2·10 9 s in air and τ ~ 5·10 9 s in vacuumapproximately two orders of magnitude larger than the best values reported previously for pchannel OFETs.
KEYWORDS:Bias stress, Single-crystals, organic n-type transistors. Over the last few years, high-quality n-type transistors based on organic semiconductors have been demonstrated 1 , with performance close to that of the best p-type devices 2 , and capable of operating under ambient conditions. Among these new n-type materials, Perylene Diimide molecules have received great attention, due to both their self-assembling properties and the tunability of the LUMO level, resulting in highly robust charge transport properties 3 . Currently, N,7 and 1,6)-dicyanoperylene-3,4:9,10-bis(dicarboximide)s (PDIF-CN 2 ) is probably the most attractive compound. Thin films can be deposited both by evaporation 4 and from solution 5 leading to high carrier mobility. Single crystal devices 6 exhibit outstanding properties, including the largest electron mobility values 7 reported for n-type organic FETs and band-like electron transport 8 . With these new molecular materials enabling top quality n-type FETs to be realized, it becomes important to explore all aspects of the device electrical characteristics that could limit the device performance.From a practical point of view, an important issue is the degradation of the field-effect transistor performance under prolonged application of a gate voltage (V GS ). This phenomenon, known as bias stress 9 , consists in the continuous decrease of the drain-source current (I DS ) when the transistor is driven in the accumulation regime. The bias stress effect has been widely investigated for p-channel devices. It was observed that the physical and chemical nature of the dielectric/organic interface plays a major role in determining the magnitude this effect 10,11 , but the precise microscopic origin of the phenomenon has remained elusive. Two possible mechanisms have been proposed for p-channel (hole accumulation) devices: one scenario attributes the effect to holes that are transferred from the FET channel to localized states in the gate insulator 11 ; another scenario invokes hole-assisted generation of protons in the presence of water, with the protons subsequently diffusing into the gate dielectric 10 . Both mechanisms lead to the accumulation of 3 positive charge (protons or holes) in the dielectric, which sc...