High frequency capacitance measurements on metal–insulator–semiconductor structures in thermal non-equilibrium condition

Sadeghi, Mahdad; Jauhiainen, Anders; Liss, B.; Sveinbjörnsson, Einar Ö.; Engström, Olof

doi:10.1016/s0038-1101(98)00220-2

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…In figure 2, we observe a very interesting capacitance ledge during forward sweeping. Such a ledge is quite similar to the ledge observed for the SiO 2 /SiC system [18]. Figure 4 shows the detailed C-V curves near the capacitance ledge.…”

Section: Resultssupporting

confidence: 75%

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Charge retention characteristics in a metal insulator semiconductor capacitor containing Ge nanocrystals

Kim

Cheong

Park

et al. 2002

Semicond. Sci. Technol.

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We investigate the charge retention characteristics in a metal-insulator-semiconductor capacitor containing Ge nanocrystals (∼3 nm in diameter) using capacitance-voltage measurements with various gate bias sweep rates. The metal-insulator-semiconductor capacitor is fabricated by pulsed laser deposition and rapid thermal oxidation. The capacitance-voltage curve shows the strong hysteresis indicating charging/discharging of carriers during the gate bias sweeping. The stored charge densities, evaluated from the flat band voltage shifts, show the non-dispersive carrier relaxation, which is a characteristic property for nanocrystals arranged in a layer. In addition, we observe an interesting capacitance ledge during forward bias sweeping. From the trap distribution determination by the Terman method, the capacitance ledge is due to an energetically localized trap at 0.33 eV + E v . The energetic position of the trap is in agreement with the ground-state hole energy level in the Ge nanocrystals. This suggests the possibility that the trap level is related to the fact that the stored charges initially tunnel out at the ground-state hole energy level.

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Section: Resultssupporting

confidence: 75%

“…Then, the interface trap density (D it ) distribution is obtained from the V g versus s relation. The interface trap density is given by [18]…”

Section: Resultsmentioning

confidence: 99%

Charge retention characteristics in a metal insulator semiconductor capacitor containing Ge nanocrystals

Kim

Cheong

Park

et al. 2002

Semicond. Sci. Technol.

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Electrical characterization of surface and interface potentials on SiC

Mizsei

Czett

2012

Applied Surface Science

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Nonvolatile memory cell effect in multilayered Ni1−xFex self-assembled nanoparticle arrays in polyimide

Jung

Kim

et al. 2006

Applied Physics Letters

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Transmission electron microscopy images showed that self-assembled Ni1−xFex nanoparticle arrays were periodically inserted in the polyimide (PI) layers. Capacitance-voltage (C-V) measurements on Al/PI/multiple-stacked Ni1−xFex nanoparticle arrays/PI/p-Si (100) structures at 300K showed a metal-insulator-semiconductor capacitor behavior with different flatband voltage shifts, which depended on the value of the sweep voltage, due to the variations of the charged electron density in the multiple-stacked Ni1−xFex nanoparticle arrays. Conductance-voltage (G-V) measurements showed that the conductance peak related to the interface trap disappeared, and that the positions of the C-V and the G-V hystereses at the sweep voltage were different.

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High frequency capacitance measurements on metal–insulator–semiconductor structures in thermal non-equilibrium condition

Cited by 3 publications

References 8 publications

Charge retention characteristics in a metal insulator semiconductor capacitor containing Ge nanocrystals

Charge retention characteristics in a metal insulator semiconductor capacitor containing Ge nanocrystals

Electrical characterization of surface and interface potentials on SiC

Nonvolatile memory cell effect in multilayered Ni1−xFex self-assembled nanoparticle arrays in polyimide

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