High-Frequency Characterization and Modeling of Low and High Voltage FinFETs for RF SoCs

Chauhan, Yogesh Singh; Kar, Anirban; Parihar, Shivendra Singh; Huang, Jun Z.; Wang, Weike; Imura, Keiichiro

doi:10.1109/edtm55494.2023.10103010

Cited by 2 publications

(1 citation statement)

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“…The continuous progression of semiconductor technology has yielded advancements in the design of SoC-based integrated circuits (ICs), resulting in enhanced operational efficiency concerning power management, layout optimization, and seamless signal integration [10][11][12][13][14][15]. The architectural framework of SoC-based designs necessitates not only optimal RF efficiency but also the amalgamation of both low-power digital blocks and high-voltage (HV) units.…”

Section: Introductionmentioning

confidence: 99%

Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Kar,

Parihar,

Huang

et al. 2024

IEEE J. Electron Devices Soc.

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Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

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