High-frequency clock operation of Josephson 256-word×16-bit RAMs

Nagasawa, Shuichi; Numata, Hideaki; Hashimoto, Y.; Tahara, S.

doi:10.1109/77.783834

Cited by 44 publications

(36 citation statements)

References 8 publications

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“…Since superconducting SFQ memories do not have large capacity [6] and cryogenic hybrid Josephson-CMOS memories are not yet available [7], we pursue a hybrid temperature-hybrid technology approach [2]. In this approach, we integrate a large capacity room-temperature semiconductor memory and a fast cryogenic RSFQ cache integrated on the same chip with an RSFQ digital signal processor.…”

Section: A Hybrid Memory Configurationmentioning

confidence: 99%

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Mukhanov

Kirichenko

Filippov

et al. 2011

IEEE Trans. Appl. Supercond.

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Results of the development of a new type of a hybrid memory for superconducting Digital-RF receivers supporting 30 Gbps memory readout speed are presented. The main feature of this memory is a combination of a high capacity room-temperature memory and a high speed on-chip superconductive cache in order to provide digital waveform templates for Digital-RF signal processing. As a room-temperature high-capacity memory with fast readout, we selected Sympuls pattern generator BMG 30 G-64 M capable of producing a 30 Gbps serial data stream of programmable pattern of 67,108,864 bits. We designed, fabricated, and tested an on-chip cache which receives high-speed template serial data from the room temperature memory and converts it into a stream of 3-bit words of template of local oscillator (LO) for digital mixer. We integrated the memory with a 1 3-bit digital I/Q mixer (1-bit digitized RF stream multiplied by 3-bit digital LO).

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Section: A Hybrid Memory Configurationmentioning

confidence: 99%

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Mukhanov

Kirichenko

Filippov

et al. 2011

IEEE Trans. Appl. Supercond.

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“…79 The design approach used in the NEC memories combine SFQ memory cells with AC-powered voltage-state Josephson periphery circuits (readout, decoder, etc.). Unfortunately, the requirement of large external AC-power limits the clock cycle to about 1 GHz, making the RAM throughput insufficient to match the much faster, DC-powered, RSFQ logic family.…”

Section: Random Access Memorymentioning

confidence: 99%

RSFQ Technology: Circuits and Systems

Brock

2001

Int. J. Hi. Spe. Ele. Syst.

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Rapid Single-Flux-Quantum (RSFQ) logic is a superconductor IC technology that, with only a modest number of researchers worldwide, has produced some of the world's highest performance digital and mixed-signal circuits. This achievement is due, in part, to a constellation of characteristics that manifest themselves at the circuit level -namely, highspeed digital logic at low-power, ideal interconnects, quantum accuracy, scalability, and simplicity of fabrication. A necessary key to translating these advantages to the systemlevel involves understanding the I/O, synchronization, and packaging issues associated with a cryogenic technology. The objective of this paper is to review the status of current RSFQ circuit-level infrastructure components and their potential impact on system-level applications.

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“…Some superconducting memory systems were demonstrated using Josephson junction (JJ) technology, which were either physically too large or had insufficient memory capacity for digital logic system applications [2], [3]. The hybrid memory was first proposed in 1993 by Ghoshal et al to solve the problem [4].…”

Section: Introductionmentioning

confidence: 99%

Simulation and Measurements on a 64-kbit Hybrid Josephson-CMOS Memory

Liu

Duzer

Meng

et al. 2005

IEEE Trans. Appl. Supercond.

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A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated by using commercially available 0.25 m and 0.35 m CMOS processes and the NEC (SRL) 2.5 kA/cm2 and UC Berkeley's 6.5 kA/cm2 Nb processes for Josephson junctions. In order to simulate the low-temperature CMOS circuits, 4 K CMOS device models are established by extracting from experiments. The measurements made at 4 K include static I-V characteristics, gate capacitances and source and drain capacitances. Details of the modeling are found in a companion paper in this issue. Performance of the high-speed interface circuits is optimized by minimizing the parasitic capacitance loading. Both the functional test and high-speed measurement for the interface circuit will be discussed. The whole structure of the memory, including interface circuit, decoder, memory cell, and Josephson read-out circuit is proposed and fabricated. From simulation, a total access time well below 1 ns is expected. The power for the whole system is about 32 mW at 1 GHz. Plans for further power and access time reduction are described.

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High-frequency clock operation of Josephson 256-word×16-bit RAMs

Cited by 44 publications

References 8 publications

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

RSFQ Technology: Circuits and Systems

Simulation and Measurements on a 64-kbit Hybrid Josephson-CMOS Memory

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