High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

Abstract

Summary A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

“…It can be observed that this design intimates an impressive improvement in FOM SR and g UGB, which allows a more expedient trade-off between speed, power, and load in [28]. This work also exhibits more remarkable small-signal driving ability than [26,[29][30][31][33][34][35] though lower than [27,28,32].…”

Low‐power class‐AB 4th‐order low‐pass filter based on current conveyors with dynamic mismatch compensation of biasing errors

“…Short‐channel CMOS devices have low intrinsic gain, and it is necessary to use cascoding to improve the accuracy of current mirrors and the open‐loop gain of the amplifiers. Cascoding increases the gain of the error amplifiers, thus reducing the output resistance of the stage, though it can limit the peak currents in class‐AB operation . The bias point is controlled by a loop, which compares the biasing current of the output stage with the desired current and injects a control current at the input of the output stage to compensate the effect of the offsets of the error amplifiers.…”

“…Cascoding increases the gain of the error amplifiers, thus reducing the output resistance of the stage, though it can limit the peak currents in class-AB operation. 5 The bias point is controlled by a loop, which compares the biasing current of the output stage with the desired current and injects a control current at the input of the output stage to compensate the effect of the offsets of the error amplifiers. The required control current is injected via a (cascoded) common source amplifier, whose gate voltage is stored on a capacitor, thus memorizing the required current.…”

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

“…By reducing the supply voltages, one of the most challenging aspects of OTA design is the CMRR. Thus, in [21][22][23], new approaches to attain high CMRR were advocated, considering low-voltage restrictions. Additionally, threshold lowering techniques have been investigated to obtain a significant reduction of minimum supply voltages [24][25][26].…”