High‐k Gate Dielectrics for CMOS Technology 2012
DOI: 10.1002/9783527646340.ch15
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High‐ k Dielectrics in Ferroelectric Gate Field Effect Transistors for Nonvolatile Memory Applications

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Cited by 10 publications
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“…The Fe-Si interface suffers from ferroelectric-silicon interdiffusion and reaction, unwanted oxide layer formation, and fatigue upon the processing. To mitigate these undesirable effects, it was proposed to use a thermodynamically stable insulating buffer layer sandwiched between ferroelectric and silicon (Lu, 2012). Different insulating oxide layers such as SiO 2 , Si 3 N 4 and Al 2 O 3 were widely investigated for metal/ferroelectric/insulator/silicon (MFeIS)-FET applications in the past few decades and a significant improvement in the electrical and ferroelectric properties have been observed (Singh et al , 2017; Singh et al , 2018a, 2018b).…”
Section: Introductionmentioning
confidence: 99%
“…The Fe-Si interface suffers from ferroelectric-silicon interdiffusion and reaction, unwanted oxide layer formation, and fatigue upon the processing. To mitigate these undesirable effects, it was proposed to use a thermodynamically stable insulating buffer layer sandwiched between ferroelectric and silicon (Lu, 2012). Different insulating oxide layers such as SiO 2 , Si 3 N 4 and Al 2 O 3 were widely investigated for metal/ferroelectric/insulator/silicon (MFeIS)-FET applications in the past few decades and a significant improvement in the electrical and ferroelectric properties have been observed (Singh et al , 2017; Singh et al , 2018a, 2018b).…”
Section: Introductionmentioning
confidence: 99%