High-k Dielectrics and Metal Gates for Future Generation Memory Devices

Abstract

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Robust High-κ Response in Molecularly Thin Perovskite Nanosheets

“…Capacitor components based on dielectric thin films are the largest elements in integrated circuits, and reducing their size and increasing their speed is an important step in the advancement of electronics. Central to these researches is the design and integration of new high-κ oxides that afford robust high-κ properties even at several nanometer thicknesses, allowing high capacitances with acceptably low leakage currents. , Extensive efforts have thus been directed at reducing their size through the use of perovskite oxides such as SrTiO 3 and (Ba 1- x Sr x )TiO 3 . However, perovskite thin films often yield reduced dielectric constants that are 1 order of magnitude smaller than bulk values. − This so-called “size effect” is a long-standing conundrum in perovskites, which severely limits their device performance. − …”

“…Central to these researches is the design and integration of new high-oxides that afford robust high-properties even at several nanometer thicknesses, allowing high capacitances with acceptably low leakage currents. 4,6 Extensive efforts have thus been directed at reducing their size through the use of perovskite oxides such as SrTiO 3 and (Ba 1-x Sr x )TiO 3 . However, perovskite thin films often yield reduced dielectric constants that are 1 order of magnitude smaller than bulk values.…”

Atomic layer deposition of perovskites part 2: Designing next generation electronic applications

“…With the reduction of thickness into the thin film regime below 50 nm, the dielectric constant decreases due to interfacial dead layer effects, where the dielectric polarization is frozen at the metal dielectric interface . So far, STO and BTO thin films are found to be ideal candidates for future DRAM applications because of the their high dielectric constants (above 120) . Table gives an overview of the dielectric properties of perovskite thin films and the factors affecting their properties.…”

Estudio DFT de los componentes de una interfaz de tres capas Hf/HfO2/TiN

“…Inorganic chemistry and material science has played an important role in the development of semiconductor industry due to the fact that parts in semiconductor applications like high-κ dielectrics gate stacks are made from perovskites and metal oxides [1]. One important application of semiconductors are information memory storage, and advances in this field require the development of novel materials [2].…”