High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

Ribes, G.; Mora, P.; Monsieur, F.; Rafik, M.; Guarin, F.; Yang, Guanghua; Roy, D.; Chang, Wenhsin; Stathis, J. H.

doi:10.1109/irps.2010.5488802

Cited by 11 publications

(10 citation statements)

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“…Some of these include digital and analog wear-out of the percolation path [8], metal filamentation (Ni, Ta-based gates) [9,10], dielectric breakdown induced epitaxy (DBIE) [11] and migration of contact metal from the source / drain ends into the channel causing a short [12,13]. Although SBD and post-BD are phenomena that have been extensively studied both from a statistical viewpoint [14] - [16] and electrical / physical analysis perspective [17] - [19] for SiO 2 /SiON and HK-IL stacks, the key limitation is that in most cases, the algorithm used to accelerate the breakdown is unable to accurately capture the transient between the percolation event and the post-BD phase, where we observe the physical morphological changes in the dielectric at the BD spot. This is due to poor compliance control.…”

Section: Introductionmentioning

confidence: 99%

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Raghavan

Padovani

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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Post breakdown (BD) reliability is an important areaof study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO 2 / SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ -interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above / below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Ǻ stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

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Section: Introductionmentioning

confidence: 99%

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Raghavan

Padovani

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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“…Based on the above results, we provide a phenomenological explanation for the bimodal Weibull distribution that resulting from an area-scaling [27][28]47]. A grain diameter of ~20 nm (Fig.…”

Section: The Role Of Gb In Bimodal Weibull Distributionmentioning

confidence: 61%

“…Weibull slope [40,42] as shown in Fig. 2 [27] proposed that the T BD of a high-κ gate stack is given by a convolution of the time to break the IL and the time to extend the BD path in the high-κ layer at the same location. The correlated high-κ BD is localized above the IL BD path; its localization does not correspond to the high-κ weakest point, thus it does not follow Poisson area scaling and gives rise to the bimodal characteristic.…”

Section: (A) (B) (C)mentioning

confidence: 99%

“…Some research groups [27][28]47] Ribes et al [27] argued that a high-κ BD would occur preferentially above the ILinitiated BD path and therefore its location may not correspond to the high-κ weakest point. Consequently, the failure distribution does not follow Poisson area scaling.…”

Section: Area-scaling Weibull Distribution Of High-κ/metal Gate Stackmentioning

confidence: 99%

“…A grain diameter of ~20 nm (Fig. 6.1) implies that many GBs would exist in the high-κ dielectric of the large area devices (~0.6 m 2 [27]). The fact that BD occurs preferentially at GBs (as evidenced in Fig.…”

Section: The Role Of Gb In Bimodal Weibull Distributionmentioning

confidence: 99%

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Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

Yew¹

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My sincere gratitude to my supervisor, Prof. Ang Diing Shenp from Nanyang Technological University (NTU), for his sound technical guidance, inspiring ideas, constructive discussions and constant encouragement throughout the course of my Ph.D research works. His immense knowledge in device physics, sharp analytical skills, effective writing skills, high research integrity and great passion in research have sparked my growing enthusiasm in research field. He is a kind and committed person, who is willing to spend time and patiently works things out with us whenever we faced difficulties in our works. Prof. D. S. Ang is more than a research supervisor to me; he has always provided me with invaluable advices, be it in research, career or life. I am very grateful and lucky to have the opportunity to work under Prof. D. S. Ang's supervision. I would like to express my sincere gratitude to Prof. Pey Kin Leong (during his tenure with NTU) for granting me access to the ultra-high vacuum scanning tunneling microscopy (UHV-STM) system and Dr. Ong Yi Ching (currently with TSMC Taiwan) for patiently training me in handling the UHV-STM system. She has been very kind to share her technical experience in the high-κ metal oxide characterization using STM. My appreciation to Dr. Lakshmi Kanta Bera for his technical advices on device fabrication process. This project is supported in part by the Singapore Ministry of Education under a research grant MOE2009-T2-1-050 and in part by the NTU.

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Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

Foissac¹,

Blonkowski²,

Kogelschatz³

et al. 2013

Microelectronics Reliability

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High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

Cited by 11 publications

References 2 publications

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

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High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

Cited by 11 publications

References 2 publications

The &#x201C;buffering&#x201D; role of high-&#x043A; in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

The &#x201C;buffering&#x201D; role of high-&#x043A; in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

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The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks