1995
DOI: 10.1007/bf02406474
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High-level algorithm and architecture transformations for DSP synthesis

Abstract: Abstract.This survey paper reviews numerous high-level transformation techniques which can be applied at the algorithm or the architecture level to improve the performance of digital signal and image processing architectures and circuits implemented using VLSI technology. Successful design of VLSI signal and image processors requires careful selection of algorithms, architectures, implementation styles, and synthesis techniques. High-level transformations can play an important role in reducing silicon area or … Show more

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Cited by 58 publications
(17 citation statements)
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“…Though traditional focus for efficient embedded processor implementation has been on optimizing code-generation techniques and hence relevant compiler technology, high-level transformations have started gaining importance because of their inherent portability and resultant boost in performance when applied appropriately ( [29], [50]). The nature of transformations can be of various kinds such as algorithmic or architectural [59], source-to-source [30] and have been studied in various contexts such as VLSI synthesis [18], DSP software synthesis [78], fault detection in parallel system [33] and so on.…”
Section: Modeling and Transformationsmentioning
confidence: 99%
“…Though traditional focus for efficient embedded processor implementation has been on optimizing code-generation techniques and hence relevant compiler technology, high-level transformations have started gaining importance because of their inherent portability and resultant boost in performance when applied appropriately ( [29], [50]). The nature of transformations can be of various kinds such as algorithmic or architectural [59], source-to-source [30] and have been studied in various contexts such as VLSI synthesis [18], DSP software synthesis [78], fault detection in parallel system [33] and so on.…”
Section: Modeling and Transformationsmentioning
confidence: 99%
“…One way to view this methodology is as a software analogue of the look-ahead and relaxed look-ahead methods used to increase pipeline parallelism in some VLSI DSP implementations [26]. Another way to view this methodology is as engineering a semigroup (that is, a set and associated closed and associative binary operation) such that repeated use of the operation results in the desired computation.…”
Section: Proposed Methodologymentioning
confidence: 99%
“…Given a dataflow graph (DFG) and architectural constraints, the HLS aims to generate the task schedule with processor assignment. Typically, the HLS performs algorithmic transformation, such as retiming, scaling, and unfolding, on the DFG to meet the architectural constraints, and allocates resources accordingly (Madisetti and Curtis, 1994;Dung and Yang, 2004;Ito et al, 1998;Parhi, 1995;Chao and Sha, 1997). Both algorithmic transformation and resource allocation require complex procedures.…”
Section: Introductionmentioning
confidence: 99%