High-level dataflow programming for real-time image processing on smart cameras

Sérot, Jocelyn; Berry, François; Bourrasset, Cédric

doi:10.1007/s11554-014-0462-6

Cited by 12 publications

(14 citation statements)

References 13 publications

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“…In Bezati et al [3] and Pelcat et al [34], top-down approaches use the data-flow model of the application to ease the parallelism exploration to target heterogeneous multi-core architectures. Other authors use a high-level programming language that implements a data-flow model of computation that is to be automatically transformed into a valid hardware implementation or multi-core software, see [41,49]. Some works rely on the UML model with its architecture specific extensions (MARTE, UML 2.0 see [25] … ) Fig.…”

Section: Hw/sw Co-design Methodologiesmentioning

confidence: 99%

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HW/SW co-design of a visual SLAM application

Piat

Fillatreau

Tortei

et al. 2018

J Real-Time Image Proc

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Vision-based advanced driver assistance systems (ADAS), appeared in the 2000s, are increasingly integrated on-board mass-produced vehicles, as off-the-shelf low-cost cameras are now available. But ADAS implement most of the timespecific and basic functionalities such as lane departure or control of the distance to other vehicles. Integrating accurate localization and mapping functionalities meeting the constraints of ADAS (high-throughput, low-consumption, and smalldesign footprint) would pave the way towards obstacle detection, identification and tracking on-board vehicles at potential high speed. While the SLAM problem has been widely addressed by the robotics community, very few embedded operational implementations can be found, and they do not meet the ADAS-related constraints. In this paper, we implement the first 3D monocular EKF-SLAM chain on a heterogeneous architecture, on a single System on Chip (SoC), meeting these constraints. In order to do so, we picked up a standard co-design method (Shaout et al. Specification and modeling of hw/sw co-design for heterogeneous embedded systems, 2009) and adapted it to the implementation of potentially any of such complex processing chains. The refined method encompasses a hardware-in-the-loop approach allowing to progressively integrate hardware accelerators on the basis of a systematic rule. We also have designed original hardware accelerators for all the image processing functions involved, and for some algebraic operations involved in the filtering process.

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Section: Hw/sw Co-design Methodologiesmentioning

confidence: 99%

“…The flow does not specify how the designer improves the knowledge along the design iterations. • fully automated design flows (see for example [41,49]) somehow fail to capture the full extent of the designer's knowledge.…”

Section: Proposed Co-design Methodologymentioning

confidence: 99%

HW/SW co-design of a visual SLAM application

Piat

Fillatreau

Tortei

et al. 2018

J Real-Time Image Proc

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“…Several authors used RVC-CAL language as a single starting point for description of SW and HW components in a heterogeneous platform [47,1,2,51]. Serot et Al [57] developed CAPH programming language for describing and implementing stream-processing applications on reconfigurable hardware, such as FPGAs. CAPH is based upon the dynamic dataflow model, supports an automated compilation producing VHDL code, and structurally reminds CAL.…”

Section: Related Workmentioning

confidence: 99%

StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

Stoutchinin

Benini

2018

J Sign Process Syst

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In this paper, we present StreamDrive, a dynamic dataflow framework for programming clustered embedded multicore architectures. StreamDrive simplifies development of dynamic dataflow applications starting from sequential reference C code and allows seamless handling of heterogeneous and applicationspecific processing elements by applications. We address issues of efficient implementation of the dynamic dataflow runtime system in the context of constrained embedded environments, which have not been sufficiently addressed by previous research. We conducted a detailed performance evaluation of the StreamDrive implementation on our Application Specific MultiProcessor (ASMP) cluster using the Oriented FAST and Rotated BRIEF (ORB) algorithm typical of image processing domain. We have used the proposed incremental development flow for the transformation of the ORB original reference C code into an optimized dynamic dataflow implementation. Our implementation has less than 10% parallelization overhead, near-linear speedup when the number of processors increases from 1 to 8, and achieves the performance of 15 VGA frames per

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“…The programmability of FPGA devices has many benefits in video processing applications due to the constant evolution of new algorithms and standards. This technology is well suited for smart cameras, where the image sampling and application-specific preprocessing are performed before data transmission to the host [8].…”

Section: Video Processing In Fpga Devicesmentioning

confidence: 99%

Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices

Trošt¹,

Žemva²

2015

Cutting Edge Research in Technologies

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Design of video processing circuits requires a variety of tools and knowledge, and it is difficult to find the right combination of tools for an efficient design process, specifically when considering open tools for evaluation or educational purpose. This chapter presents an overview of video processing requirements, programmable devices used for embedded video processing and the components of a video processing chain. We propose a novel design flow for generating customizable intellectual property IP cores used in streaming video processing applications. This design flow is based on domain-specific modules in Python language. Examples of generated cores are presented.

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High-level dataflow programming for real-time image processing on smart cameras

Cited by 12 publications

References 13 publications

HW/SW co-design of a visual SLAM application

HW/SW co-design of a visual SLAM application

StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices

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