High-level decision diagram manipulations for code coverage analysis

Minakova, K.; Reinsalu, Uljana; Chepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund; Ellervee, Peeter

doi:10.1109/bec.2008.4657515

Cited by 5 publications

(3 citation statements)

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“…The experiment benchmarks several designs from ITC'99 benchmarks family [ 23 ] and a design gcd which is an implementation of the greatest common devisor. Figure 9 shows comparison results obtained in [ 10 ] with the proposed methodology, based on different HLDD representations and coverage analysis, achieved by a commercial state-of-the-art HDL simulation tool from a major CAD vendor using the same sets of stimuli.…”

Section: Resultsmentioning

confidence: 99%

Application of high-level decision diagrams for simulation-based verification tasks

Jenihhin¹,

Raik²,

Chepurov³

et al. 2010

Estonian J. Eng.

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This paper describes the advantages of the application of a system representation model, called High-Level Decision Diagrams (HLDDs), for hardware functional verification. Two tasks of simulation-based verification, considered in this paper, are assertion checking and code coverage analysis. Assertion checking employs temporal extension of an existing HLDD model aimed at supporting temporal properties, expressed in Property Specification Language (PSL). The described approach to code coverage analysis provides for more accurate results than traditional VHDL code coverage methods. Experimental results show the feasibility and efficiency of the HLDDsbased approaches.

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Section: Resultsmentioning

confidence: 99%

Application of high-level decision diagrams for simulation-based verification tasks

Jenihhin¹,

Raik²,

Chepurov³

et al. 2010

Estonian J. Eng.

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show abstract

“…A comparison between the existing high level decision diagram (HLDD) based model [20] and the proposed model on the statement and branch coverage metrics is provided in the Table VII. In all the cases, experiments are run on a Computer with AMD Phenom(tm) II X3710 Processor, 2.5 GHz, 4.0 GB of RAM, Windows XP Professional Service Pack 2. The test patterns are generated using SMT solver and executed for the custom-built circuits on the Xilinx version 10.1 simulator.…”

Section: Resultsmentioning

confidence: 99%

“…In this paper, five fundamental code coverage metrics: statement, condition, branch, path, and expression [17] are included. Recent works [18], [19], [20], [21], [22], [23], [24] have addressed design verification with a number of code coverage metrics. Though the approaches defined and analyzed code coverage metrics well to measure the quality of test benches (stimuli) but does not guarantee full confidence in correctness with respect to specification of a DUT.…”

Section: Introductionmentioning

confidence: 99%

Beyond test pattern generation: Coverage analysis

Bhowmik

Deka

Biswas

2015

2015 International Conference on Industrial Instrumentation and Control (ICIC)

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The size and complexity of the very large scale integrated circuits are ever increasing because of rapid advancements of deep-submicron and nanometer technologies. It has become imperative to address and attack the problems associated with verification at earlier design stages. The paper proposes a high level design verification scheme for the circuits designed at the behavioral level. The scheme is based on selection of a goal node in a control flow graph representation of a design under test. The scheme focuses on generation of suitable test patterns that adds gaining confidence in correctness of the design via code coverage metrics. The scheme does complete verification for a design in two attempts. First time verification attempts testing that exercises a set of test patterns to ensure the correctness. Second time verification involves code coverage analysis with the generated test patterns that accounts amount of correctness of the design. Experiments have been accomplished on a number of custombuilt as well as ITC'99 benchmark circuits and establish the scalability of the proposed scheme. Experimental results establish the fact that high code coverage guarantees quality circuit design.

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Novel Method to Generate Tests for VHDL

Jusas

Neverdauskas

2013

Communications in Computer and Information Science

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High-level decision diagram manipulations for code coverage analysis

Cited by 5 publications

References 5 publications

Application of high-level decision diagrams for simulation-based verification tasks

Application of high-level decision diagrams for simulation-based verification tasks

Beyond test pattern generation: Coverage analysis

Novel Method to Generate Tests for VHDL

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