High level estimation of the area and power consumption of on-chip interconnects

Langen, Dominik; Brinkmann, André; Rückert, Ulrich

doi:10.1109/asic.2000.880753

Cited by 21 publications

(8 citation statements)

References 3 publications

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“…The delay through a multiplexer tree is accurately approximated by summing the intrinsic delay of all stages and the delay of one cell driving the cumulative capacitive load of one vertical wire of length , and for is given by (21) In a very accurate model, the delay of the source DFF and the capacitive load of the destination DFF that define the critical path should be considered in (21). The clock period in nanoseconds is given by the sum of (20) and (21), to yield (22) For sufficiently large , the clock rate is given by (23) The previous equations are based on the assumption where all cells have equal drive strength. The power dissipated in a wire is independent of the drive strength of the cell driving the wire, hence this assumption does not affect the power dissipated in the wires.…”

Section: Analysis Of the Conventional Crossbarmentioning

confidence: 99%

“…While other power models for crossbar switches have been presented, i.e., [20]- [22], they have not used parameters from real CMOS standard cell libraries, and therefore do not provide designers with critical data on their designs implemented in a particular CMOS technology. The analytic methodology developed in this paper is general and useful for the accurate architectural evaluation of electrical and optoelectronic crossbar switches, given a specific standard cell library.…”

Section: Introducti/onmentioning

confidence: 97%

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Power complexity of multiplexer-based optoelectronic crossbar switches

Szymański

Gourgy

2005

IEEE Trans. VLSI Syst.

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The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-m CMOS technology is illustrated. The pipelined switch design occupies 70 mm 2 of CMOS area, and consumes 80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.

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Section: Analysis Of the Conventional Crossbarmentioning

confidence: 99%

Section: Introducti/onmentioning

confidence: 97%

Power complexity of multiplexer-based optoelectronic crossbar switches

Szymański

Gourgy

2005

IEEE Trans. VLSI Syst.

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“…3) subject to, Eqs. (4), (6), (7), (8), and 9The data transfer delay CLT I for each task c with bus width r is evaluated using Eq. (1).…”

Section: Co-synthesis Algorithmmentioning

confidence: 99%

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Pandey¹,

Drechsler²

2008

2008 Design, Automation and Test in Europe

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In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.

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“…A packet switch fabric circuit is an on-chip interconnect network [Langen et al, 2000]. The power consumption on switch fabrics comes from three major sources: 1) the internal node switches; 2) the internal buffer queues; and 3) the interconnect wires.…”

Section: Power Modeling With Bit Energymentioning

confidence: 99%

“…The switch fabric circuit is the fundamental building block inside a network router, it distributes all network traffic from ingress ports to egress ports shown in Figure 2.1 [Langen et al, 2000]. The performance of switch fabrics is very critical in network applications.…”

Section: Introductionmentioning

confidence: 99%

Cross-Layer Design for Energy Efficiency on Data Center Network

Cheocherngngarn¹

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High level estimation of the area and power consumption of on-chip interconnects

Cited by 21 publications

References 3 publications

Power complexity of multiplexer-based optoelectronic crossbar switches

Power complexity of multiplexer-based optoelectronic crossbar switches

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Cross-Layer Design for Energy Efficiency on Data Center Network

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