High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors

Paul, JoAnn M.; Thomas, Donald E.; Cassidy, Andrew

doi:10.1145/1080334.1080335

Cited by 29 publications

(12 citation statements)

References 25 publications

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“…The Modeling Environment for Software and Hardware (MESH) permits performance and power evaluation when threads execute on sets of heterogeneous resources under a variety of custom schedulers [123], [124]. MESH explores CHM design above the level of the ISS, where designers deal with threads, processors, and memories instead of instructions, functional units, and registers.…”

Section: • Easy Debuggingmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

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Section: • Easy Debuggingmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…This paper describes two improvements to MESH that allow it to efficiently model asynchronous events such as device interrupts and preemptive scheduling: interrupt modeling (Section 4.1) and lightweight consume calls (Section 4.2). For more detailed explanations of other aspects of the MESH environment we refer the interested reader to Paul et al [2005].…”

Section: Overview Of Meshmentioning

confidence: 99%

Interrupt modeling for efficient high-level scheduler design space exploration

Johnson

Paul

2008

ACM Trans. Des. Autom. Electron. Syst.

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Single Chip Heterogeneous Multiprocessors executing a wide variety of software are increasingly common in consumer electronics. Because of the mix of real-time and best effort software across the entire chip, a key design element of these systems is the choice of scheduling strategy. Without task migration, the benefits of single chip processing cannot be fully realized. Previously, high-level modeling environments have not been capable of modeling asynchronous events such as interrupts and preemptive scheduling while preserving the performance benefits of high level simulation. This paper shows how extensions to Modeling Environment for Software and Hardware (MESH) enable precise modeling of these asynchronous events while running more than 1000 times faster than cycle-accurate simulation. We discuss how we achieved this and illustrate its use in modeling preemptive scheduling. We evaluate the potential of migrating running tasks between processors to improve performance in a multimedia cell phone example. We show that by allowing schedulers to rebalance processor loads as new tasks arrive significant performance gains can be achieved over statically partitioned and dynamic scheduling approaches. In our example, we show that system response time can be improved by as much as 1.96 times when a preemptive migratory scheduler is used, despite the overhead incurred by scheduling tasks across multiple processors and transferring state during the migration of running tasks. The contribution of this work is to provide a framework for evaluating preemptive scheduling policies and task migration in a high level simulator, by combining the new ability to model interrupts with dramatically increased efficiency in the high-level modeling of scheduling and commuincation MESH already provides.

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“…MESH [8] is a high level environment for exploring different multiprocessor system on chip architectures. Performance is based on user specified instruction counts for threads executing on processors.…”

Section: Design Automation and Test Europe (Date)mentioning

confidence: 99%

Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor

Meyerowitz¹,

Sangiovanni-Vincentelli²,

Sauermann³

et al. 2008

2008 Design, Automation and Test in Europe

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A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing accuracy. This simulator is API-compatible with the multiprocessor's operating system. Therefore, it can compile and run unmodified applications on the host PC. This flow has been implemented for MuSIC(Multiple SIMD Cores) [6], a heterogeneous multiprocessor developed at Infineon to support Software Defined Radio (SDR). When compared with an optimized cycle-accurate VP of MuSIC on a variety of tests, including a multiprocessor JPEG encoder, the accuracy is within 20%, with speedups from 10x to 1000x.

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High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors

Cited by 29 publications

References 25 publications

Capacity metric for chip heterogeneous multiprocessors

Capacity metric for chip heterogeneous multiprocessors

Interrupt modeling for efficient high-level scheduler design space exploration

Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor

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