High-level power estimation techniques in embedded systems hardware: an overview

Abstract

Power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited power budget systems (battery-operated hand-held devices, electro-optical pluggable modules, IoT and green energy systems, etc.). Subsequently, early power consumption estimation at design time is crucial for power optimization. The aim of this paper is to present an overview of High-Level power estimation techniques currently available along with a comprehensive comparison between different methodologies and their applications on estimated models. When high speed and high performance are key features of a specific embedded system, increase in energy consumption becomes the main hurdle to be tackled while keeping speed/performance v/s power consumption trade-off at a minimum. This paper provides designers, interested in power consumption modeling, with knowledge on how to select best power estimation techniques applied to designated target models.

An Overview of Energies Problems in Control and Robotic Systems

“…Based on all energy reduction solutions stand the embedded systems. Embedded systems can reduce power consumption in the plant (system) since they are integrated, but also fasten the energy optimization techniques [5]. In this paper Richa et al review the power consumption of Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC).…”

“…The system designer has to consider keeping the speed/performance versus the power consumption trade-off at a minimum. In [5] there are presented the optimization methods for the following components:…”

“…Embedded systems as the basis of control systems of robots, unmanned aerial vehicles, and automation systems (since their introduction) had a very important design parameter, which is to keep the power consumption as low as possible. For the embedded system components there are presented several energy optimization methods in [5]:…”

“…This possibility is given by all Computer Aided Design (CAD) tools and also by the FPGA and SOC development tools. This possibility was also analyzed in [5] and gives estimation error of power estimation between 5% to 55% or higher depending on the component types.…”

“…• Measurement-based methods are a common approach for the already implemented hardware and use several built-in onboard and on-chip sensors. The estimation error is mentioned only for microprocessors and SOC -estimated to be higher than 30% for one core and higher than 4% for 16 cores [5] Richa et al [5] gave a detailed discussion about the power estimation methods, which were analyzed on several criteria such as: hardware and software dependency, circuit characterization based on modeling, estimation effort, estimation error, modeling effort, and modeling levels. Embedded system power consumption is divided into dynamic and static power consumption.…”