High-level programming of coarse-grained reconfigurable architectures

Abstract

We propose that, in order to meet high computational demands, the application development has to be based on suitable models of computations that will lead to scalable and reusable implementations. The models should enhance the understanding of the application and at the same time enable the developer to organize the computations so that they can be efficiently mapped to the target reconfigurable architecture. The goal of the thesis is to propose methods to program future coarse-grained reconfigurable architecttures in a productive manner in such a way as to achieve energy efficient mapping with improved performance.<p>©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.</p>Embedded Parallel Computin