High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips

Menichelli, Francesco; Menicocci, Renato; Olivieri, Mauro; Trifiletti, Alessandro

doi:10.1109/tdsc.2007.70234

Cited by 26 publications

(9 citation statements)

References 22 publications

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“…Concerning the simulation of an IC's EM side-channel radiation, a few papers have put forward some ideas using Hamming Distance, Hamming Weight or improved models [9]. The existing models have several drawbacks, including not scalable for very large designs, not considering real hardware implementations, etc.…”

Section: Rtl Em Side Channel Radiation Modelmentioning

confidence: 99%

Golden chip free Trojan detection leveraging electromagnetic side channel fingerprinting

Liu

Yuan

et al. 2019

IEICE Electron. Express

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Side channel based hardware Trojan detection is one of the most investigated schemes to ensure the trustworthiness of integrated circuits (ICs). However, nearly all of the side-channel methods require a golden chip reference, either a trusted fabricated circuit or layout, which is very difficult to access in reality. In this paper, we propose a golden chip free electromagnetic (EM) side channel simulation and statistical Trojan detection framework. We utilize the design data at early stage of the IC lifecycle to generate EM radiation, and the generated EM traces serve as the golden reference. In order to leverage the EM signatures, a neural network algorithm is utilized for Trojan detection. Experimental results on selected AES benchmarks on FPGA show that the proposed method can effectively detect Trojans with the presence of noise and variations.

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Section: Rtl Em Side Channel Radiation Modelmentioning

confidence: 99%

Golden chip free Trojan detection leveraging electromagnetic side channel fingerprinting

Liu

Yuan

et al. 2019

IEICE Electron. Express

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“…Another important research direction is that of designing tools for high-level side-channel attack simulation developed with the aim of automating analysis techniques to help a cryptanalyst identify possible implementation vulnerabilities with minimal effort on their side. In [22], an approach is presented based on the SystemC 2.0 language [1], the de facto standard in complex digital system simulations illustrated by a case study of analyzing various implementations of AES [23] algorithm.…”

Section: Software Tools For Cryptanalysismentioning

confidence: 99%

Modeling Security Threats to Cryptographically Protected Data

Savelieva¹,

Avdoshin²

2009

Proceedings of the Spring/Summer Young Researchers' Colloquium on Software Engineering

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In this paper, we introduce a mathematical model of threats for analyzing the security of cryptographic systems based on risk management principles. We also provide economic indicators as a basis to build a rationale for investments to cryptographic systems. Some points of designing software tools to support our methodology are covered in the paper. The new approach that incorporates the threat model, automatic cryptographic strength verification tools and economic techniques, is instrumental for providing sound arguments to choose a cryptographic system and for implementing an information security strategy. An overview of alternative approaches is provided along with the results of comparative analysis revealing their drawbacks as compared to the method presented in this paper.Index Terms-risk management, threat modeling, cryptographic system, discounted cash flow.

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“…Only recently, systematic methods support design for trust and security have been described in literature [5].Menichelli et. al present an exploration approach centered on high level simulation based on SystemC to suggest improvements in the knowledge and identification of the weaknesses in cryptographic algorithm implementations [6]. Ardeshiricham et.…”

Section: Introductionmentioning

confidence: 99%

PASCAL: Timing SCA Resistant Design and Verification Flow

Lai

Jenihhin

Raik

et al. 2019

2019 IEEE 25th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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A large number of crypto accelerators are being deployed with the widespread adoption of IoT. It is vitally important that these accelerators and other security hardware IPs are provably secure. Security is an extra functional requirement and hence many security verification tools are not mature. We propose an approach/flow -PASCAL -that works on RTL designs and discovers potential Timing Side Channel Attack (SCA) vulnerabilities in them. Based on information flow analysis, this is able to identify Timing Disparate Security Paths that could lead to information leakage. This flow also (automatically) eliminates the information leakage caused by the timing channel. The insertion of a lightweight Compensator Block as balancing or compliance FSM removes the timing channel with minimum modifications to the design with no impact on the clock cycle time or combinational delay of the critical path in the circuit.

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High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips

Cited by 26 publications

References 22 publications

Golden chip free Trojan detection leveraging electromagnetic side channel fingerprinting

Golden chip free Trojan detection leveraging electromagnetic side channel fingerprinting

Modeling Security Threats to Cryptographically Protected Data

PASCAL: Timing SCA Resistant Design and Verification Flow

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