High-level synthesis challenges and solutions for a dynamically reconfigurable processor

Abstract

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone finite state machine and that switches "contexts" consisting of many operational and storage units in processing elements (PEs) and wires between them. Utilizing the resources not only in two spatial dimensions but also vertically (time-multiplexed) under accurate timing and area constraints imposes challenges for a high-level synthesizer for the DRP. We describe a C-based behavioral synthesis method which features data path generation with clock speed optimization. This is achieved by including the overhead of selectors in the scheduling algorithm, and considering a wire delay at each PE level. A new technique is introduced to achieve high area efficiency. It works by effectively allocating multiple steps into the context. From the original highlevel synthesizer for application-specific integrated circuits, some of the basic rules such as operator and register sharing were completely changed due to the coarse grained and multi-context architecture. Experimental results show that the generated data paths are highly parallelized and well balanced between contexts. The delay controllability enables the highest throughput point to be found more easily.

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

“…As opposed to our paper, [25] does not investigate the complex interdependency between timing violations and resource overuse, while [26] and [27] only allow chaining in particular cases: pairs of neighboring cells and cells in a fully connected stripe, respectively.…”

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors

“…An integrated design environment called Musketeer [14], which includes a high level synthesis tool, a design mapper for DRP, simulators, and a layout/viewer tool, is provided. Applications can be written in a C-based high level hardware description language called Behavioral Design Language (BDL), synthesized, and mapped directly onto the DRP-1 chip for executing.…”

“…The example is described in NEC's BDL [14], a C-based language. r, l i (i = 0, 1, 2, 3) are arrays of register and memory types with 16-bit width.…”

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

“…In SA-C [5], a set of data-parallel semantics are defined to hide the reconfigurable hardware details, however, the performance still relies on the programmer's capability and runtime configuration executable file could not be generated. High level compilers, e.g., Garp C compiler [6], NEC electronics' Musketeer [7] and Template-based compiler [8] are also proposed recently. In all these compilers, partitioning the computations between the processor and an RPU (hardware part) is a necessity of the compiling flow.…”