High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Socha, Petr; Miškovský, Vojtěch; Novotný, Martin

doi:10.1016/j.micpro.2021.104311

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…When we design masked AES circuits and consider security, a better performing circuit provides higher side-channel attack resistance. Additionally, in this study, the masked AES circuits do not possess sufficient security features, which is different from the observations in previous work such as [23]- [25]. One reason for this is that our evaluation is based on simulation.…”

Section: Evaluation Of Aes Circuits Without Maskingmentioning

confidence: 59%

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Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits

Mizuno

Nishikawa

Kong

et al. 2023

IJRES

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<span>Many internet of things (IoT) devices and integrated circuit (IC) cards have been compromised by side-channel attacks. Power-analysis attacks, which identify the secret key of a cryptographic circuit by analyzing the power traces, are among the most dangerous side-channel attacks. Gen-erally, there is a trade-off between execution time and circuit area. However, the correlation between security and performance has yet to be determined. In this study, we investigate the cor-relation between side-channel attack resistance and performance (execution time and circuit area) of advanced encryption standard (AES) circuits. Eleven AES circuits with different performances are designed by high-level synthesis and logic synthesis. Of the eleven AES circuits, six are circuits with no side-channel attack countermeasures and five are circuits with masking countermeasures. We employ four metrics based on a T-test to evaluate the side-channel attack resistance. The results based on the correlation coefficient show the correlation between side-channel attack resistance and performance. The correlation varies according to four metrics or masking countermeasure. We argue that designers should change their attitudes towards circuit design when considering security.</span>

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Section: Evaluation Of Aes Circuits Without Maskingmentioning

confidence: 59%

“…Blömer et al [24] showed that there may be a weakly masking countermeasure. However, the masked program [23] quoted in this paper was guaranteed to be secure in [25]. The algorithm of AES without masking countermeasure is shown in Figure 2.…”

Section: Figure 1 Experimental Flow Thai Is Circuit Design Power Anal...mentioning

confidence: 99%

Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits

Mizuno

Nishikawa

Kong

et al. 2023

IJRES

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“…Additionally, we selected block ciphers, AES(-v1), PRESENT and Serpent from [7] as benchmarks. We also selected the open-source AES(-v2) from the Vitis Library [14].…”

Section: A Benchmarksmentioning

confidence: 99%

“…Thus, we propose to use static analysis to detect weaknesses in HLS-generated RTL and an automated repair flow to correct detected weaknesses by generating HLS directives that enable changes to the RTL without modifying the high-level code. We evaluate our work on synthetic benchmarks that highlight how similar high-level patterns can yield different RTL designs and conduct a case study analyzing three block ciphers (AES, serpent, and PRESENT from [7]) to explore the weaknesses that can be introduced by a commercial HLS tool. We show that we can detect these weaknesses automatically and provide fixes to the designers.…”

Section: Introductionmentioning

confidence: 99%

Using Static Analysis for Enhancing HLS Security

Collini,

Ah-Kiow,

Pilato

et al. 2024

IEEE Embedded Syst. Lett.

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Due to the increasing complexity of modern integrated circuits, High-Level Synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLSgenerated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being 3× to 200× faster.

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Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis

Koufopoulou

Xevgeni

Papadimitriou

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation

Cited by 6 publications

References 5 publications

Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits

Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits

Using Static Analysis for Enhancing HLS Security

Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis

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