High-Level Synthesis for FPGAs: From Prototyping to Deployment

Abstract

Abstract-Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR).

Exploiting vectorization in high level synthesis of nested irregular loops

“…For example if(c_31) has to be modified in such way that the new condition is true if at least one of the element of the vector version of c 31. This is obtained by creating a new condition c 31[0] || c 31 [1].…”

“…Design by hand efficient hardware implementations can be a hard task since requires the knowledge of hardware description languages which is typically a rare expertise. To overcome or at least to mitigate this issue, High Level Synthesis [1] has been introduced: it consists of a (semi)-automatic design flow, potentially composed of several methodologies, that starting from a high level representation of a specification (e.g., a C/C++ source code implementation) produces its hardware implementation.…”

Embedded Implementation of VHR Satellite Image Segmentation

“…In Equation (24), since a D2Q5 model is used in the design, we have D = 2 and b = 5. The length of each link in the active contour model is defined as 1, so c = 1.…”

Compilation and architecture support for customized vector instruction extension

“…The input to this flow is the original C file. After applying the customization compilation flow introduced in Section III, the selected patterns are passed to AutoPilot [9] to be synthesized. The output of AutoPilot contains the timing information of the custom vector instruction when implemented in hardware.…”