High-Level Synthesis for Self-Timed Systems

Yang, Jung-Lin; Tien, Hsu-Ching; Hsu, Chia-Ming; Lin, Sung-Min

doi:10.1109/apccas.2006.342465

Cited by 2 publications

(1 citation statement)

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“…The ST control unit is based on FIFOs that contain micropipelines of asynchronous control blocks (ACB) using the 4-phase single rail protocol (Jung-Lin, Hsu-Ching, Chia-Ming, & Sung-Min, 2006;Ortega, Gurrola, Raygoza, Pedroza, & Terrazas, 2009). This protocol is used because communication is more effective than 2-phase single rail protocol on FPGAs, as it fulfills the necessary characteristics for substituting synchronous FIFOs.…”

Section: Asynchronous Microprocessor Structurementioning

confidence: 99%

Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices

Crúz¹,

Baron²,

Cisneros³

et al. 2015

Journal of Applied Research and Technology

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This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous.

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Section: Asynchronous Microprocessor Structurementioning

confidence: 99%