High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Campbell, Keith A.; Vissa, Pranay; Pan, David Z.; Chen, Deming

doi:10.1145/2744769.2744851

Cited by 16 publications

(4 citation statements)

References 18 publications

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“…Burak et al [14] proposed an Enhanced Duplication (ED) technique to provide error detection by utilizing unused bits of registers to store the duplication of narrow values. Keith et al [15] proposed a low-cost error detection approach by leveraging the flexibility of the binding and scheduling phases in the HLS process to perform lightweight modulo-3 arithmetic computing on the data-path design. Approximate circuit designs at different levels of VLSI design abstractions have been widely studied [9], [10].…”

Section: Motivational Examplementioning

confidence: 99%

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Zhu

Schäfer

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Many applications tolerate errors at their outputs. Some examples include image and digital signal processing applications. At the same time these applications are often used in systems that require high degrees of fault-tolerance. Examples include autonomous driving applications. Thus, in this work we propose a method to reduce the complexity of hardware redundant systems that are amenable to approximate computing such that soft errors outside a maximum specified threshold are detected. This leads to the detection of catastrophic errors, while allowing the system to continue functioning when smaller single event upsets (SEU) occur. The proposed method reduces the complexity of the duplicated module by applying a set of approximations in such a way that the output is guaranteed to operate within a given error range with the exact module. Experimental results show that the proposed approach works well and that area saving between 30% and 19% can be achieved on average for different error ranges compared to the traditional exact duplication with compare approaches.

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Section: Motivational Examplementioning

confidence: 99%

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Zhu

Schäfer

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Utilizing a high-level synthesis (HLS) engine from UIUC [5], 12 accelerator designs derived from the PolyBench benchmark suite [42] were evaluated with protection using LEAP-DICE (circuit), logic parity (logic), modulo-3 shadow datapaths (architecture), EDDI (software), and ABFT (algorithm) techniques. Note that, software and algorithm techniques are converted into hardware checkers during high-level synthesis.…”

Section: Resilience Exploration For Custom Acceleratorsmentioning

confidence: 99%

Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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“…In [158], structural DMR is proposed which can detect soft error and correct the error significantly with lesser logic complexity in comparison to traditional TMR. Another low cost approach is presented to detect error for arithmetic data paths by performing light-weight shadow computation in modulo-3 space [159].…”

Section: Soft Error Related Reliabilitymentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

Self Cite

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Cited by 16 publications

References 18 publications

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Cross-Layer Resilience Against Soft Errors: Key Insights

Design for manufacturability and reliability in extreme-scaling VLSI

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