High-Level Synthesis: Past, Present, and Future

Martín, Grant; Smith, Geoff

doi:10.1109/mdt.2009.83

Cited by 252 publications

(113 citation statements)

References 8 publications

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“…Even though HLS tools have been developed for decades, only the tools developed in the last decade have gained a more widespread interest. The main reasons for this are the use of an input language, such as C, familiar to most designers, the good quality of results and their focus on digital signal processing (DSP) [23]. HLS tools are especially interesting in the context of rapid prototyping where they can be used for architecture exploration and to produce designs with different parameters.…”

Section: Implementation Of Ls Mmse and Sage Channel Estimationmentioning

confidence: 99%

Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM

Ketonen

Juntti

Ylioinas

et al. 2013

J Sign Process Syst

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Channel estimation algorithms and their implementations for mobile receivers are considered in this paper. The 3GPP long term evolution (LTE) based pilot structure is used as a benchmark in a multiple-input multipleoutput (MIMO) orthogonal frequency division multiplexing (OFDM) receiver. The decision directed (DD) spacealternating generalized expectation-maximization (SAGE) algorithm is used to improve the performance from that of the pilot symbol based least-squares (LS) channel estimator. The performance is improved with high user velocities, where the pilot symbol density is not sufficient. Minimum mean square error (MMSE) filtering is also used in estimating the channel in between pilot symbols. The pilot overhead can be reduced to a third of the LTE pilot overhead with DD channel estimation, obtaining a ten percent increase in data throughput. Complexity reduction and latency issues are considered in the architecture design. The pilot based LS, MMSE and the SAGE channel estimators are implemented with a high level synthesis tool, synthesized with the UMC 0.18 μm CMOS technology and the performance-complexity trade-offs are studied. The MMSE estimator improves the performance from the simple LS estimator with LTE pilot structure and has low power consumption. The SAGE estimator has high power consumption but can be used with reduced pilot density to increase the data rate.

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Section: Implementation Of Ls Mmse and Sage Channel Estimationmentioning

confidence: 99%

Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM

Ketonen

Juntti

Ylioinas

et al. 2013

J Sign Process Syst

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“…Sustained by the increasing need to start the design and validation of multi-core SoCs at higher levels of abstraction (system-level design) [5], the use of high-level synthesis (HLS) is gaining consensus [11]: indeed, there are now several commercial HLS tools which are capable to take a single Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: Introductionmentioning

confidence: 99%

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

Bombieri

Liu

Fummi

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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We present a method to automatically generate a synthesizable C++ specification from the given RTL design of an IP block, by abstracting away most of its micro-architectural characteristics while preserving its functionality. The goal is twofold: recover the IP block specification for system-level design, and enable the derivation of more optimized implementations through high-level synthesis.The C++ specification can be generated with different interfaces thus allowing the IP model to be reused across different system platforms. Experimental results show that the proposed approach not only enhances the reusability of the recovered IP block but also unveils a richer design space to explore.

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“…The resulting hardware descriptions can be implemented directly into circuits like FPGAs. Hardware engineers may not modify them and so economize in the design process time (Martin and Smith, 2009). Such time gain can be used in the test and the on-chip verification steps.…”

Section: Introductionmentioning

confidence: 99%

“…These parameters oblige designers to follow different design flows (Martin and Smith, 2009) and to find alternative solutions especially against timing constraints like Real-Time Operating System (RTOS), Multi-Processors System On Chip (MPSoC) or the hardware implementation of several parts of the electrical process (e.g., controller unit). Still also, some design methodologies which are dedicated to the hardware design field, are more and more adopted and applied to the process control one like hardware-software CoDesign using languages like SystemC or SpecC (Salewski and Kowalewski, 2008).…”

Section: Introductionmentioning

confidence: 99%

“…HiL testing phase is essential in the validation process of control units and motor drives. In addition, prior works are focused on two major axes (1) FPGA implementation of complex control algorithms for performance purposes (2) Validation of electrical controllers and/or motors at earlier stages of production for cost reasons (Martin and Smith, 2009). These approaches don't consider the validation and the diagnosis of the electrical process after the production stage.…”

Section: Introductionmentioning

confidence: 99%

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Design of Field Programmable Gate Array Based Emulators for Motor Control Applications

Taha¹

2012

American Journal of Applied Sciences

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Problem statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs. However, exploiting these platforms requires deep hardware conception skills and remains an important time consuming stage in a design flow. High Level Synthesis technique avoids this bottleneck and increases design productivity as witnessed by industry specialists. Approach: This study proposes to apply this technique for the conception and implementation of a Real Time Direct Current Machine (RTDCM) emulator for an embedded control application. Results: Several FPGA-based configuration scenarios are studied. A series of tests including design and timing-precision analysis were conducted to discuss and validate the obtained hardware architectures. Conclusion/Recommendations: The proposed methodology has accelerated the design time besides it has provided an extra time to refine the hardware core of the DCM emulator. The high level synthesis technique can be applied to the control field especially to test with low cost and short delays newest algorithms and motor models.

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High-Level Synthesis: Past, Present, and Future

Cited by 252 publications

References 8 publications

Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM

Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

Design of Field Programmable Gate Array Based Emulators for Motor Control Applications

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