Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium 2006
DOI: 10.1109/ipdps.2006.1639477
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High-level synthesis with reconfigurable datapath components

Abstract: High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high… Show more

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Cited by 3 publications
(3 citation statements)
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“…A heuristic scheduling algorithm, which utilizes reconfigurable datapath components, has been presented in [19]. In this case, the resulting schedule is shortened so that the gain in execution clock cycles compensates the configuration time overhead.…”
Section: Related Workmentioning
confidence: 99%
“…A heuristic scheduling algorithm, which utilizes reconfigurable datapath components, has been presented in [19]. In this case, the resulting schedule is shortened so that the gain in execution clock cycles compensates the configuration time overhead.…”
Section: Related Workmentioning
confidence: 99%
“…Reconfigurable computing for HLS is reported in [1] and [5]. In [1] the problem of register binding of the RTL description is considered and a technique to utilize on-chip embedded memory (found in modern FPGA devices) for this task is proposed.…”
Section: Related Researchmentioning
confidence: 99%
“…In [1] the problem of register binding of the RTL description is considered and a technique to utilize on-chip embedded memory (found in modern FPGA devices) for this task is proposed. In [5] a scheduling heuristic is proposed, offering shorter schedules but requiring many and frequent PRTRs, which may impose impractical overhead when applied to traditional reconfigurable devices. In fact, the solution of [5] is aimed toward future architectures with very small reconfiguration time.…”
Section: Related Researchmentioning
confidence: 99%