High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement

Abstract

In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC) enhancement is proposed in this paper. The efficient correlated double sampling (CDS) method in pixels is used to optimize the noise characteristics of the ROIC and output CDS voltage to the column bus. An AC enhancement method is proposed to quickly establish the column bus signal, and an adaptive offset compensation method is used at the column bus terminal to eliminate the nonlinearity caused by the pixel source follower (SF). Based on the 55 nm process, the proposed method is comprehensively verified in an 8192 × 8192 IR ROIC. The results show that, compared with the traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full well capacity is increased from 4.3 Me- to 6 Me-. The row time of the ROIC is reduced from 20 µs to 2 µs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and the single-column power consumption of the readout optimization circuit is 33 μW in the accelerated readout mode and 16.5 μW in the nonlinear correction mode.

High Dynamic Pixel Structure Based on an Adaptive Integrating Capacitor

“…In this paper, the nonlinear correction circuit proposed in the literature [25] is used in the post-stage readout circuit so that the CDS signal is equal to the voltage across the variable integrating capacitor, Vgs in Equation ( 6). Thus, Equation ( 6) can be written as As shown in Figure 2, the variation of C int has only one distinct inflection point near the threshold voltage over the range of V gs from 0 V to 2.4 V and therefore can be approximated to be segmentally linear.…”

“…In this paper, the nonlinear correction circuit proposed in the literature [25] is used in the post-stage readout circuit so that the CDS signal is equal to the voltage across the variable integrating capacitor, V gs in Equation ( 6). Thus, Equation ( 6) can be written as Equation (10).…”

“…It can be seen that V CDS is not strictly linear with i ph , but it can be approximated as such. This paper adopts a nonlinear correction circuit of replicating FD nodes proposed in the literature [25], which can perfectly solve the problem of non-linearity caused by the source follower. For the post-stage readout circuit, although the output of each stage of the readout circuit cannot be completely linear, the non-linearity of the post-stage readout circuit has been verified to be only 1%.…”

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors

“…Several notable studies have previously investigated the sources of nonlinearity in 4T pixels. Through improvements in circuit structure and methods such as digital calibration, these works have successfully mitigated the nonlinear response, achieving a final output linearity exceeding 99.95% [ 9 , 10 , 11 ]. Within the linear region, nonlinearity is mainly caused by the variation in electrical parameters with voltage, such as the small-signal voltage gain of the source follower (SF) and the capacitance of the FD (C FD ) node [ 12 ].…”

“…In these studies, the optimization methods can be divided into the analog domain and digital domain. Achieving an extremely high linearity is mostly realized through digital domain; however, digital calibration is a method that consumes significant chip space and power [ 9 ]. This underscores that the optimization at the existing hardware level is still insufficient for the design of high-linearity pixels.…”