High-linearity Radiation-hardened Segmented 12-bit Digital-to-analog Converter Using Binary-weighted Switches

Kochetkov, Dmitriy; Gorchakova, Maria; Enns, Aleksandr V.; Kachura, Sergey A.; Belousov, Egor

doi:10.1109/elconrus51938.2021.9396690

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…A 16-bit SAR register is made of 16 D flip-flops connected in series fashion. The SAR logic generates the digital code for the DAC in each comparison stage [39]. At the end of the conversion cycle, an output register outputs The waveform of each SAR-register bit (s0 to s15) represents the evolving approximation of the input signal in real-time as shown in the below figure 21.…”

Section: Sarmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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Section: Sarmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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Optogenetics Micro LED Light Source Driver Circuit Design

Wang

2022

2022 16th ICME International Conference on Complex Medical Engineering (CME)

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High-linearity Radiation-hardened Segmented 12-bit Digital-to-analog Converter Using Binary-weighted Switches

Cited by 2 publications

References 5 publications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Optogenetics Micro LED Light Source Driver Circuit Design

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High-linearity Radiation-hardened Segmented 12-bit Digital-to-analog Converter Using Binary-weighted Switches

Cited by 2 publications

References 5 publications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Optogenetics Micro LED Light Source Driver Circuit Design

Contact Info

Product

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications