High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Royer, C. Le; Damlencourt, J.-F.; Vincent, Benjamin; Romanjek, K.; Cunff, Y. Le; Grampeix, H.; Mazzocchi, V.; Carron, V.; Fabrice, Nemouchi; Hartmann, Jean‐Michel; Arvet, C.; Vizioz, C.; Tabone, C.; Hutin, Louis; Batude, P.; Vinet, M.

doi:10.1016/j.sse.2011.01.012

Cited by 13 publications

(3 citation statements)

References 16 publications

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“…One of the attractive features is that localized ultra-thin GeOI can be fabricated by condensation, on SOI [105,106] and even on a bulk Si wafer [107]. In this way, GeOI pMOSFETs can be combined with SOI nMOSFETs for obtaining high mobility CMOS [108].…”

Section: Ultra-thin Ge Channel Quantum Well and Fin-type Pmosfetsmentioning

confidence: 99%

Challenges and opportunities in advanced Ge pMOSFETs

Simoen

Mitard

Hellings

et al. 2012

Materials Science in Semiconductor Processing

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Section: Ultra-thin Ge Channel Quantum Well and Fin-type Pmosfetsmentioning

confidence: 99%

Challenges and opportunities in advanced Ge pMOSFETs

Simoen

Mitard

Hellings

et al. 2012

Materials Science in Semiconductor Processing

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“…Therefore, in order to improve the performance of CMOS based circuits, devices with high mobility materials have been considered [11]. A novel concept of hybrid CMOS (HCMOS) has been proposed by many researchers which consists of a pMOS and an nMOS with different channel materials such as Ge and Si respectively [12][13][14]. However, many theoretical and experimental studies have reported that SiGe exhibits higher electron mobility than Si and hence, can behave as a substitute for n-type Si devices in HCMOS [9].…”

Section: Introductionmentioning

confidence: 99%

Device and circuit level analysis of negative capacitance hybrid CMOS: a prospect for low power/low voltage applications

Bansal¹,

Kaur²

2019

Semicond. Sci. Technol.

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In this work, a concept of negative capacitance hybrid CMOS (NCHCMOS) is presented which consists of p-NCGeOIFET (NC germanium-on-insulator FET) and n-NCSiGeOIFET (NC SiGeon-insulator FET). Both devices have been simulated by using respective calibrated TCAD models with Landau-Khalatnikov equation. The enhanced performance of both devices due to NC effect has been shown in terms of improved barrier and subsequently reduced leakage current (by 2 orders). The max gain of Ge and SiGe NCFETs has been found to be 1.64 and 1.56 (i.e.>1) respectively which is manifested in reduced subthreshold swing values. Results have also shown that the NC of ferroelectric material attributes to very high gate capacitance which is further responsible for enormous increase in on-state current (170% in p-NCGeOIFET and 103% in n-NCSiGeOIFET). Further, to investigate the performance of these devices in low power/low voltage applications, static and transient characteristics of NCHCMOS based gates and circuit have been obtained. It has been shown that NCHCMOS gives improved circuit performance in terms of high noise margin, reduced rise and fall time, less propagation delay, and reduced power and energy dissipation as compared to HCMOS. It is also displayed that NCHCMOS exhibits very less values (approximately by an order or 2) of energy-delay-product in respect to HCMOS and provides energy efficient operation.

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“…Conventionally, the integration of III-V semiconductors with silicon is based on the heteroepitaxial growth of multi-layered structures on silicon or a variety of wafer bonding techniques. [7][8][9][10][11] The devices based on such structures combine the high carrier mobility and high luminescence efficiency of III-V semiconductors with the well-developed silicon technology. The main obstacles towards the mass production of such hybrid systems are related to the difficulties of the direct growth of III-V semiconductors on silicon, such as polar/non-polar surface incompatibility, large lattice mismatch, and differences between thermal expansion coefficients of III-V materials and Si.…”

Section: Introductionmentioning

confidence: 99%

III-V/Si on silicon-on-insulator platform for hybrid nanoelectronics

Prucnal

Zhou

et al. 2014

Journal of Applied Physics

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The unique properties of SOI wafers enable the integration of heterogeneous materials with distinct functionalities in different layers. In particular, III-V compound semiconductors are very attractive for low-noise and high-speed electronic and photonic components integrated on a single chip. We have developed a CMOS compatible and fully integrated solution for the integration of III-V compound semiconductors with silicon technology for optoelectronic applications. InAs compound semiconductor nanostructures are synthesized in SOI wafers using the combined ion beam implantation and millisecond liquid-phase epitaxial growth. Optoelectronic and microstructural investigations carried out on implanted, annealed, and selectively etched samples confirm the formation of high-quality III-V compound semiconductor nanostructures. V C 2014 AIP Publishing LLC. [http://dx.

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High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Cited by 13 publications

References 16 publications

Challenges and opportunities in advanced Ge pMOSFETs

Challenges and opportunities in advanced Ge pMOSFETs

Device and circuit level analysis of negative capacitance hybrid CMOS: a prospect for low power/low voltage applications

III-V/Si on silicon-on-insulator platform for hybrid nanoelectronics

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