Compared with conventional silicon (Si)-based Pulse Width Modulation (PWM) rectifiers, PWM rectifiers based on silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have significant technical advantages and broad application prospects in terms of efficiency and power density, inherited from the high-speed switching feature. However, high-speed switching also induces gate-source voltage interference, which impacts the overall character of the conversion system. This paper considered the impact of gate-source voltage interference on loss, revealing an efficiency optimization for all-SiC PWM rectifiers. Firstly, this paper theoretically investigated the mechanism of improving the conversion system efficiency by using the 4-pin Kelvin packaged SiC MOSFETs. Then, based on the industrial product case study, loss distribution, using different package styles, was quantitatively analyzed. Finally, experiment test results verified the efficiency improvement of the PWM rectifier with the 4-pin Kelvin package SiC MOSFETs.Energies 2020, 13, 1421 2 of 17 interference exceeds the switching loss reduction obtained by the high-speed switching, it makes no sense to increase the switching speed further.Many works of literature have discussed the gate-source voltage interference issue, mostly in phase-leg configuration. Zhang et al. [16] discussed the design of the digital isolator and the layout of Printed Circuit Board (PCB). A higher switching speed causes PWM signal distortion through the parasitic capacitance of the isolator. The distorted PWM signals may induce device gate-source voltage interference, and the optimized PCB layout would suppress this gate-source voltage interference. The limit of switching speed is given based on the mechanism of common-mode noise induced by parasitic capacitances in the isolator. The method of adding a shielding layer to the input channel of the isolator and adopting the Kelvin grounding structure is proposed to suppress the interference [17,18]. The crosstalk issue is another kind of gate-source voltage interference [19]. The drain-source voltage change of SiC MOSFET is coupled by Miller capacitance, which changes the displacement current, affects the gate current, and causes the gate-source voltage interference.For the suppression of the gate-source voltage interference issue, two methods are presented by Zhang et al [20]. Firstly, gate impedance regulation (GIR), which is an auxiliary circuit composed of one active device and a capacitor to reduce the gate impedance during the switching transients. Secondly, gate voltage control (GVC), which is an auxiliary circuit consisting of two active devices and one diode, pre-charging the gate-source capacitance before the switching transient. In the follow-up research, Zhang et al. [21] proposed an intelligent gate drive (IGD), where the auxiliary circuit is composed of two active devices and two diodes, to actively control the gate-source voltage and gate impedance under different switching transients. Active miller cl...