High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder

Peng, Xiao; Chen, Zhixiang; Zhao, Xiongxin; Maehara, Fumiaki; Goto, Satoshi

doi:10.1109/asap.2010.5540964

Cited by 13 publications

(7 citation statements)

References 7 publications

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“…However, for supporting multiple code lengths and further reconfigurability, QSN network is required. 14 introduced a variant of the Banyan network that similar to the QSN network can support cyclical shifts for Z ≤ N. As shown in Figure 4, in this network, a duplicate of the original Banyan network and an additional multiplexer stage are added to the design. For an N Â N switch with Z active inputs and shift value SV, the original network shifts inputs by SV, whereas the duplicate network shifts by SV + (N À Z).…”

Section: Shift Networkmentioning

confidence: 99%

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Pourjabar

Choi

2021

Circuit Theory & Apps

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This paper presents a partially parallel low-density parity-check (LDPC) decoder for the 5G New Radio (NR) standard. The design is using a multiblock parallel architecture with a flooding schedule. The decoder can support any code rates and code lengths up to the lifting size Z max = 96. To compensate for the dropped throughput associated with the smaller Z values, the design can double and quadruple its parallelism when lifting sizes Z ≤ 48 and Z ≤ 24 are selected, respectively. Therefore, the decoder can process up to eight frames and restore the throughput to the maximum. To facilitate the design's architecture, a new variable node for decoding the extended parity bits existing in the lower code rates is proposed. The FPGA implementation of the decoder results in a throughput of 2.1 Gbps decoding the 11/12 code rate. Additionally, the synthesized decoder using the 28-nm TSMC technology achieves a maximum clock frequency of 526 MHz and a throughput of 13.46 Gbps. The core decoder occupies 1.03 mm 2 , and the power consumption is 229 mW.

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Section: Shift Networkmentioning

confidence: 99%

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Pourjabar

Choi

2021

Circuit Theory & Apps

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“…Based on the user input parameters, the controller further calculates shift right value (SR_sectionj) of the left shifter and shift left value (SL_sectionj) of the right shifter for each section by following ( 10)- (11).…”

Section: Alternative Sectioned Version Of Segmented Reconfigurable Cyclic Shiftermentioning

confidence: 99%

“…Part of hardware stays in idle if the input data size is not the maximum. The extended barrel-shifter design in [9][10][11] can perform cyclic shift of multiple input data, yet the data size and shift value must be the same.…”

Section: Introductionmentioning

confidence: 99%

Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder

Lam

Qiu

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In various wireless communication standards, such as Wi-Fi, WiMAX, and 5G standards, QC-LDPC decoders are required to decode a codeword of variable length. Part of the decoder is in idle if the length of codeword is not the maximum. A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder. If the shifter can only shift one input at a time, the QC-LDPC decoder can only decode one codeword at a time as well. A segmented reconfigurable cyclic shifter is proposed in this paper to enable a QC-LDPC decoder to parallelly decode multiple codewords. The proposed shifter can be reconfigured into multiple segments of different sizes. Each segment can perform a cyclic shift of different shift values independently. Therefore, the proposed shifter can enhance the QC-LDPC decoder to decode multiple codewords parallelly by inputting another codeword (or codewords) to re-activate the idle hardware. The test chip of QC-LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in 0.18-μm CMOS technology which can parallelly decode six codewords.

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“…The work described in [68] portrays a highly parallel shuffle network based on the ByN paradigm. Like the BeN, also ByN is bound to a power-of-two number of inputs: as Oh and Parhi have done in [63], also here the introduction of 3 × 3 switches allows to handle WiMAX standard various submatrix sizes.…”

Section: Shift and Shufflementioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder

Cited by 13 publications

References 7 publications

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder

Flexible LDPC Decoder Architectures

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