High performance 2D transform hardware for future video coding

An FPGA implementation of future video coding 2D transform

“…Energy consumptions of the FPGA implementations of FVC baseline and reconfigurable 2D transform hardware proposed in [13], the proposed FVC 2D transform hardware and the HEVC 2D DCT hardware for one frame of each video are shown in Fig. 4.…”

“…The proposed FPGA implementation of FVC 2D transform is compared with FPGA implementations of FVC 2D transform hardware and HEVC 2D DCT hardware in the literature [13]- [16]. The comparison is shown in Table IV.…”

“…Since the FVC baseline and reconfigurable 2D transform hardware proposed in [13] implement multiplications with constants using adders and shifters, their FPGA implementations are slower and use more Slices, LUTs and DFFs than the proposed FPGA implementation of FVC 2D transform. However, they do not use any DSP blocks.…”

“…Two FVC 2D transform hardware are proposed in the literature [13]. They implement FVC 2D transform operations for 4x4 and 8x8 TU sizes by applying 1D transforms in vertical and horizontal directions.…”

Interpolation Filter Design Based on All-Phase DST and Its Application to Image Demosaicking

“…In addition to DCT-II and 4 × 4 DST-VII, which are adopted in HEVC [2], an adaptive multiple transform (AMT) scheme is used for residual coding for both inter-coded and intra-coded blocks. VVC uses five DCT/DST-based transform types known as DCT-II, DCT-V, DCT-VIII, DST-I, and DST-VII; and employs 4 × 4, 8 × 8, 16 × 16, 32 × 32, and 64 × 64 TU sizes [4]. The JVET established the first draft of the VVC standard specification and the VVC test model 1 (VTM1) encoding method at its 10th meeting (10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) April 2018, San Diego, CA, USA).…”