High performance a‐IGZO thin‐film transistors with mf‐PVD SiO 2 as an etch‐stop‐layer

ECS J. Solid State Sci. Technol.

Bhoolokam

Chasin

et al. 2015

Self Cite

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as fieldeffect mobility (μ FE ), sub-threshold slope (SS −1 ) and current ratio (I ON/OFF ) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however significant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (V TH ) shifts compared to TFTs with PECVD ESL when stressed under a gate field of +/−1 MV/cm for duration of 10 4 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer. Amorphous oxide semiconductors (AOSs) are gaining traction to replace the a:SiH in TFTs applied in liquid crystal display (LCD) and organic light-emitting diode display (OLED) backplanes. These oxide semiconductor have high transparency and relatively high electron mobility in the amorphous state. An additional advantage lies in the low process temperature required for AOS integration on plastic film and so potentially enabling flexible transparent display and electronics. Among many AOSs, a-IGZO is the most promising due to its high mobility, excellent uniformity, and the compatibility with transparent and flexible substrate, as compared to conventional amorphous and polycrystalline silicon.1-8 For either LCD or OLED displays with IGZO backplane, bottom-gate top-contact (BGTC) ESL configuration is preferred. The ESL protects the a-IGZO back channel from damages caused during the source-drain metallization and patterning.9-11 The damage-free surface improves the bias stabilities especially at accelerated bias stress conditions under illumination. However commonly the ESL is deposited by plasma assisted CVD processes to which a-IGZO can be sensitive.12 Therefore there is a need to investigate the effect of the ESL on the characteristics of a-IGZO TFTs.PECVD based SiO 2 deposited at temperature higher than 350• C using SiH 4 /N 2 O chemistry is commonly used as an ESL in Flat-PanelDisplay (FPD) industry due to its fast deposition rate, high uniformity and good step coverage. For the integration on commercialized flexible substrates like PEN or polyimide, deposition and process temperature should be lower to prevent shrinkage of the plastic foil and allow easy de-lamination. It is known that PECVD layer deposited at lower temperature deteriorate layer quality leading to lower density, higher amount of dangling bonds and an increase in the amount of hydrogen incorporated into the SiO 2 layer. The poor density and increase of hydrogen is problematic for a-IGZO TFTs because it leads to uncontrolled doping density. [13][14] Few research groups have demonstrated the use of PVD based dielectrics (SiO 2 and Al 2 O 3 ) as passivation layer or ESL as an altern...

Section: Resultsmentioning

confidence: 59%

Section: Resultsmentioning

confidence: 99%

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Medium Frequency Physical Vapor Deposited Al₂O₃and SiO₂as Etch-Stop-Layers for Amorphous Indium-Gallium-Zinc-Oxide Thin-Film-Transistors

ECS J. Solid State Sci. Technol.

Bhoolokam

Chasin

et al. 2015

Self Cite

“…Future displays will require increased resolution (4k2k) and high frame-rate (120 Hz) which demands low parasitic capacitance and high speed switching thin-film transistors (TFTs). Amorphous oxide semiconductors (AOSs) TFTs with large gate-source/drain (S/D) overlap like in conventional back-channel-etch (BCE) and etchstop-layer (ESL) configurations are less suitable [3][4]. Selfaligned (SA) TFT configuration as introduced by Sony [5] is preferred.…”

Section: Introductionmentioning

confidence: 99%

P‐6: Impact of Buffer Layers on the Self‐Aligned Top‐Gate a‐IGZO TFT Characteristics

Symp Digest of Tech Papers

Bhoolokam

Müller

et al. 2015

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In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self-aligned (SA) top gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFT characteristics. Finally an optimized layer was integrated in TFT backplane on polyimide (PI) foil and a QQVGA AMOLED display is demonstrated.

“…3640 × 2160 pixels) and frame rates (120 or 240 Hz) require high speed TFTs. The established back-channel-etch and etch-stop-layer configuration-based TFTs are less suitable for such applications due to their high parasitic capacitance caused by the overlap between the source and drain electrodes (S/Ds) and the gate electrode [5,6]. The self-aligned (SA) TFT configuration presents benefits such as reduced overlap capacitance and a smaller footprint, and is therefore preferred.…”

Section: Introductionmentioning

confidence: 99%

Low-temperature formation of source–drain contacts in self-aligned amorphous oxide thin-film transistors

Journal of Information Display

Müller

Steudel

et al. 2015

Self Cite

We demonstrated self-aligned amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistors (TFTs) where the source-drain (S/D) regions were made conductive via chemical reduction of the a-IGZO via metallic calcium (Ca). Due to the higher chemical reactivity of Ca, the process can be operated at lower temperatures. The Ca process has the additional benefit of the reaction byproduct calcium oxide being removable through a water rinse step, thus simplifying the device integration. The Ca-reduced a-IGZO showed a sheet resistance (R SHEET ) value of 0.7 k /sq., with molybdenum as the S/D metal. The corresponding a-IGZO TFTs exhibited good electrical properties, such as a field-effect mobility (μ FE ) of 12.0 cm 2 /(V s), a subthreshold slope (SS −1 ) of 0.4 V/decade, and an on/off current ratio (I ON/OFF ) above 10 8 .