High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Qu, Yun R.; Prasanna, Viktor K.

doi:10.1109/tpds.2015.2389239

Cited by 76 publications

(45 citation statements)

References 18 publications

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“…We compared our design with TCAM [17], FSBV [18] and StrideBV [19] with respect to the average memory requirement per flow in table 1. The BV-based pipelined architecture [8] is unclear for the amount of memory requirement, but usually the BV algorithms can provide high throughput at the cost of low memory efficiency. As can be seen, our design consumed 44.5 bytes per flow, achieving a memory efficiency of 1 byte of memory for each byte of flow.…”

Section: Memory Efficiencymentioning

confidence: 99%

High-performance architecture for flow-table lookup in SDN on FPGA

Hatami

Bahramgiri

2019

J Supercomput

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We propose Range-based Ternary Search Tree (RTST), a tree-based approach for flow-table lookup in SDN network. RTST builds upon flow-tables in SDN switches to provide a fast lookup among flows. We present a parallel multi-pipeline architecture for implementing RTST that benefits from high throughput and low latency. The proposed RTST and architecture achieve a memory efficiency of 1 byte of memory for each byte of flow. We also present a set of techniques to support dynamic updates. Experimental results show that RTST can be used to improve the performance of flow-lookup. It achieves a throughput of 670 Million Packets Per Second (MPPS), for a 1 K 15-tuple flow-table, on a state-of-the-art FPGA.

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Section: Memory Efficiencymentioning

confidence: 99%

High-performance architecture for flow-table lookup in SDN on FPGA

Hatami

Bahramgiri

2019

J Supercomput

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“…The entry has the label value as the l2 destination and wildcard for other fields. Also the corresponding action of the rule is to send the packet to a specified port on the switch [25]. It is an open source network emu lator that creates a network consists of Switches, Controlle r and Hosts.…”

Section: Deploying Fuzzy Logic Controlled System (Flcs) In Contrmentioning

confidence: 99%

Design of Fuzzy-Based Traffic Provisioning in Software Defined Network

Bhandari¹,

Singh²

2016

IJITCS

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Abstract-This Software defined networks helps to realize extraordinary services that can be easily embedded in network operations of switch. It provokes the decomposition of the control and data planes. The control plane is more extensible, as it is unproblematic to change or introduce any new functionality into the network. It is studied that any new integration can be easily added up with a very low line of code (LOC). The work proposes a fuzzy based approach for traffic provisioning in SDN. Fu zzy Logic Control System (FLCS) is a controller co mp rising of two fuzzy systemsLabel Switched Path setup System (LsS) and Traffic Splitting System (TSS). The co mputation of dynamic status of Load and Delay is utilized by LsS to arrange the paths in preference order. The attained Link Capacity and Utilizat ion Rate are emp loying by TSS for maintain ing congestion free path. Created three different topologies and performed ping reachability test and executed iperf testing tool for performance analysis on Mininet framework.The impact of this is to facilitate better decision making for splitting the traffic for different capable paths. Simulat ion setup is deployed using OpenFlow Switches and Controllers to study their performance. The packet delivery rat io remained above 98% , showing rare chances of congestion and delay was below than 2.6 seconds with TTL in range of 60-80 milliseconds.

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“…Each rule can have one or more fields and their associated value, and an action to be taken if matched. To perform the needed comparison to each packed, FPGA has been successfully used [46], [47], [48]. In [49] we find a comparison between packet classification implementations in FPGA, GPP and GPU, with an impressive advantage to FPGA.…”

Section: Fpga and Network Securitymentioning

confidence: 99%

Future Internet and Reconfigurable Computing:Considerations on Flexibility and Security

Mesquita¹,

Frosi²

2016

J. Inf. Secur. Cryptogr.

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<div data-canvas-width="547.27795779347">The Future Internet is expected to support services in both existing and new scenarios, in terms of mobility, quality, scalability and security, among other. In this work we present how reconfigurable Computing (RC) may contribute to build Future Internet (FI) flexibility and security. Therefore, we discuss some aspects of FI initiatives that can be addressed by Reconfigurable Computing. Then we show some features of the Reconfigurable Computing enabling technology – FPGA – which can help to build a more flexible and secure Future Internet. The concluding remarks concern the need to bring together FI and RC researchers.</div>

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High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Cited by 76 publications

References 18 publications

High-performance architecture for flow-table lookup in SDN on FPGA

High-performance architecture for flow-table lookup in SDN on FPGA

Design of Fuzzy-Based Traffic Provisioning in Software Defined Network

Future Internet and Reconfigurable Computing:Considerations on Flexibility and Security

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