High performance and energy efficient FinFET based 1-bit PT full adders

Saraswathi, Ch.; Rani, N. Usha; Nagateja, T.

doi:10.1109/iccic.2016.7919605

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…In contrast to CMOS logic, pass-transistor logic, which consists of pass transistors or pass gates, has been of great interest due to its advantage in the number of transistors. Since [9] first proposed a PTL-based FA circuit in 1992, a variety of PTL-based full adders have been proposed [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…However, upon its implementation in a 4-bit adder, the maximum delay was recorded at 1.095 ns. A diode-connected FinFET restorer (D-FinFETs) was proposed in [11] to eliminate a drawback of the replication of full swing in the PTL-based FA. Although the D-FinFETs effectively mitigated certain drawbacks of PTL, they incurred substantial delays and additional power consumption.…”

Section: Introductionmentioning

confidence: 99%

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Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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“…Full adder is most crucial component in arithmetic logic unit (ALU) which is used in computers, processors, communication devices, etc. Various design methods are adopted by researchers to design full adder circuits [1,2,3,4]. Shannon decomposition based technique [5] has been proposed for a power efficient full adder circuit.…”

Section: Introductionmentioning

confidence: 99%

Design of power efficient stable 1-bit full adder circuit

Subramaniam

Singh

Murthy

2018

IEICE Electron. Express

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High speed and low power hybrid adder using 22 nm SG-TG FinFET

Arora,

Tripathi,

Raj

2024

Phys. Scr.

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This paper demonstrates a new 22-T (transistor) hybrid adder for low-power applications using 22nm shorted gate (SG) tri-gate (TG) FinFET technology. Large conducting channels and increased gate control make FinFET suitable for high-speed low-power computing circuits. The proposed hybrid adder is designed using pass transistor and CMOS logic. Also, it adopts the state-of-the-art techniques of dynamic leakage balancing on the ground path and stacking ground transistors that reduce parasitic effects and increase the speed of the logic transitions compared to traditional designs. Extensive simulations were executed to characterize for PDP (Power Delay Product), power dissipation, and delay of the hybrid adder circuit. From the Monte Carlo analysis, the robustness and efficiency of the circuit are also observable for minimum variation in power and delay due to process voltage and temperature (PVT) variations. Besides, concerning the supply variability and temperature, the circuit shows excellent stability by keeping the power consumption and delay performance consistent. The proposed 22-T hybrid adder using 22nm SG-TG FinFET are very well-suited in low power and high-speed processors showing highly stable behaviour with reduced process variability.

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High performance and energy efficient FinFET based 1-bit PT full adders

Cited by 4 publications

References 8 publications

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Design of power efficient stable 1-bit full adder circuit

High speed and low power hybrid adder using 22 nm SG-TG FinFET

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