High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Tateshita, Y.; Wang, J.; Nagano, K.; Hirano, Takuichi; Miyanami, Y.; Ikuta, Tetsuya; Kataoka, Toshihiko; Kikuchi, Yoshihiro; Yamaguchi, S.; Ando, Tetsu; Tai, K.; Matsumoto, Ryusaku; Fujita, S.; Yamane, Chigusa; Yamamoto, Ryo; Kanda, Shigenobu; Kugimiya, K.; Kimura, Tomonori; Ohchi, Tadayuki; Yamamoto, Y.; Nagahama, Y.; Hagimoto, Yoshiya; Wakabayashi, Hitoshi; Tagawa, Y.; Tsukamoto, Masanori; Iwamoto, Hayato; Saito, Masao; Kadomura, S.; Nishida, Naoki

doi:10.1109/iedm.2006.346959

Cited by 24 publications

(10 citation statements)

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“…The stress memorization technique [17], [18], which is typically used to improve NMOS speed, relies on plastic deformation of certain materials due to a process step and the consequent memorization of the applied stress in the channel. Finally, in the hybrid orientation technique [12], [14], crystal orientations are used to separately enhance NMOS and PMOS speeds.…”

Section: A Stress Modulation Techniques In Processmentioning

confidence: 99%

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Kahng

Sharma

Topaloglu

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source-shallow trench isolation (STI)-has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We conduct process simulation of a 65-nm production STI technology to generate mobility and delay impact models for STI stress. We then utilize these models to perform STI-stress-aware delay analysis of critical paths using Simulation Program with Integrated Circuit Emphasis (SPICE). We present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation and active-layer fill insertion to improve complementary metal-oxide-semiconductor performance. We assess the proposed analysis and optimization on small designs implemented with a 65-nm production cell library and a standard synthesis place-and-route flow. Our stress-aware timing analysis improves the clock frequency by 4.68% to 6.31% over traditional worst case analysis, and our optimization improves clock frequency by 2.44% to 5.26%. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wire length.

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Section: A Stress Modulation Techniques In Processmentioning

confidence: 99%

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Kahng

Sharma

Topaloglu

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Many binary metal oxides, such as NiO, HfO 2 , TiO 2 , have been proposed as insulator layers for the MIM structure of RRAM devices due to their ease of composition control and fabrication [5][6][7][8][9][10][11][12][13]. HfO 2 is of particular interest due to its compatibility with the conventional ''complementary metal oxide-semiconductor'' (CMOS) manufacturing process [14,15]. On the other hand, the potential radiation hardness of RRAM devices has also attracted attention for aerospace and nuclear plant applications [16][17][18][19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Study of radiation hardness of HfO2-based resistive switching memory at nanoscale by conductive atomic force microscopy

Lin

Hwang

et al. 2015

Microelectronics Reliability

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“…High-dielectric-constant materials (high-k) have been applied as gate dielectrics in metal-oxide-semiconductor field-effect transistors (MOSFETs) to reduce gate leakages and to improve short channel effects (SCEs). In addition to a conventional structure, which is high-k-first/metal-first, [1][2][3] two other structures, that is, high-k-first/metal-last, 4) and high-k-last/metal-last structures, [5][6][7] have been studied so far. The high-k-last/metal-last structures have attracted a great deal of attention because they have advantages such as mobility enhancement, 8,9) selectivity of the gate electrode to control threshold voltage (V th ), and low thermal budget of the gate dielectric.…”

Section: Introductionmentioning

confidence: 99%

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

Kikuchi¹,

Wakabayashi²,

Tsukamoto³

et al. 2011

Jpn. J. Appl. Phys.

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For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

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High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Cited by 24 publications

References 0 publications

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Study of radiation hardness of HfO2-based resistive switching memory at nanoscale by conductive atomic force microscopy

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

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