High performance BiCMOS circuit technology VLSI gate arrays

Yee,; Chau,; Wang, Hong; Davis, Sharon G.; Moore, Nicholas J.; Chas,; Lemonds,; Eklund,; Havemann,; Bonifield,; Graham,; Pozadzides,; Shah, Pankaj

doi:10.1109/vlsic.1989.1037463

Cited by 4 publications

(2 citation statements)

References 1 publication

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“…More specifically, BICMOS, a leading edge technoloev is attracting the attention of many researchers due to its advantages: large drive capability, higher clock speed, low-powel dissipation, increased packing density, multiple U 0 level availability etc. Multiplier structures based on MBA and Wallace trees are reported recently using static as well as dynamic logic schemes [19,20]. It is important to note that the enhanced output drive capability of the BiCMOS technology can be exploited to solve the large fan out problem associated with the array multipliers based on MBA or CSA.…”

Section: Introductionmentioning

confidence: 99%

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Poornaiah¹,

Mohan²,

Ahmad

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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In this paper, we present the design of a novel BiCMOS/Bipolar concurrent multiplier-accumulator (BICMAC) architecture that can be configured on-the-fly for selecting multiply alone or multiplyaccumulation (add/subtract) computations involving unsigned/signed 2's compliment/mixed-mode data formats for normal as well as extended precision arithmetic. The proposed BICMAC does not require the use of a separate adder module normally used in the conventional MACS thereby achieving approximate reductions of 50% and 20%, respectively, in the computation time and area making it attractive for VLSI implementation. It can be used as a fundamental computing block of the algorithmically specialized integrated circuits, like, systolic and wavefront array processors for an efficient implementation of the computationally intensive DSP functions: FIRDIR filtering, correlation, matrix multiplication etc., resulting in reduced hardware complexity and latency. The technology independent nature of the proposed architecture makes it attractive also for VLSI implementation using fast emerging contemporary technologies: GaAs (MESFET, HEMT, JET) and HBT.

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Section: Introductionmentioning

confidence: 99%

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Poornaiah¹,

Mohan²,

Ahmad

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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“…Gate arrays are becoming an increasingly important application for BiCMOS technology [3]. Compared to CMOS, the high output drive capability of the bipolar device can be used to minimize the delay of heavily loaded gates.…”

Section: Process Performancementioning

confidence: 99%

A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

Eklund

Chapman

Wei

et al.

International Technical Digest on Electron Devices Meeting

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This paper describes a 0.5 jLm BiCMOS technology for high performance logic and SRAM's which is capable of supporting 5 V "hot carrier hard" circuit designs. In these designs the maximum drain-to-source voltage across a 0.5 jLm NMOS device is restricted to 4 V to ensure hot carrier reliability using 12 nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5 V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 picosee/picoFarad which is 30% smaller than the load drive factor for the same basic design gate built using an O.S jLm proceS8 with 20 nm gate oxide. The paper also discusses how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5 jLm BiCMOS process. The addition of these components permits a 23 jLm2 stacked 6-T CMOS SRAM cell to be realized, suitable for 4Mbit-clas8 BiCMOS SRAM's.

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Process technology for submicron BiCMOS VLSI

Haken

IEEE International Symposium on Circuits and Systems

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High performance BiCMOS circuit technology VLSI gate arrays

Cited by 4 publications

References 1 publication

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

Process technology for submicron BiCMOS VLSI

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