High-performance bulk CMOS technology for 65/45nm nodes

Subthreshold voltage high-k CMOS devices have lowest energy and high process tolerance

“…Recent research has shown that process variation can greatly affect the functionality of logic gates [16]. It can also bring in uncertainties in the circuit logic.…”

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

“…In an effort to reduce EOT, past investigations attempted metal and metal nitrides [50,52,57,94,99,100,109,126,128] and metal silicides [96,106,108,128] for the gate conductor, in order to overcome the unavoidable depletion in polysilicon gates [151,152]. Cumulative experimental research also indicates that there might be noise due to tunneling from polysilicon gate into high-k dielectrics or charge trapping and defects at this interface [97,99,126,153,154], or remote scattering caused by Coulomb coupling between gate trap and MOS channel (oxide is thin and single excess charge at gate side of the oxide is "visible" as a local, e.g.…”

“…Fortunately, the constructive conservatism in commercial technologies prevents from the randomness in the empirical research and keeps the noise in the desired lower half of the distribution, as illustrated with diamonds in this plot. However, this conservatism results in a slowdown of device scaling [152], as was predicted in the past [3], because the costs of modifications for using metal gates are high and the predictability and repeatability of multilayer gate stacks are not certain, since no scalable model is currently available for these gate stacks. Thus, the risk is mostly moved in the research, and the commercial fabricators implement the modifications gradually and very carefully, as one can see in [152] for Fujitsu, for example, although the main reason is not the low-frequency noise, actually.…”