High-performance circuit design for the RET-enabled 65-nm technology node

Liebmann, Lars W.; Barish, Arnold; Baum, Zachary M. C.; Bonges, Henry A.; Bukofsky, S.; Fonseca, Carlos; Halle, Scott; Northrop, Gregory A.; Runyon, Steven L.; Sigal, L.

doi:10.1117/12.538242

Cited by 42 publications

(37 citation statements)

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“…where K 1 = Ce D∆X and K 2 = A∆X + B. In this model, ∆X, ∆Y , and ∆H are depicted in Figure 16; A, B, C, D, and n parameters are fitted to give < 0.8nm ∆H error with measured data from printed-image simulations on a fairly wide range of practical corner-dimensions 11 as shown in Figure 17. Simple geometric approximations are then used to infer the gate-length and gate-width variations from the ∆H values caused by the rounding of each corner (in the diffusion and poly layers).…”

Section: Variabilitymentioning

confidence: 99%

“…CDU value in the table is for 2D-poly patterning. For 1D fixed-pitch poly, we use CDU 3σ improvement factor of 47% over 2D-poly reported by IBM in [11] and assume that half the improvement is from poly being unidirectional and the other half is from the poly pitch being fixed.…”

Section: A Testing Setupmentioning

confidence: 99%

“…In our framework, CDU is described by a distribution, which captures the dependency on dose and focus variations. Pattern dependency is captured by using different CDU 3σ values for each poly-patterning style including 1D/2D patterning and multiple/fixed pitch, which can seriously impact CDU [11,41,42].…”

Section: Variabilitymentioning

confidence: 99%

“…Finally, the drive current variability index is calculated using Equation 8. 11 The fitting of the model is performed only once per technology node. The model can be fitted to early printed-image simulations or actual silicon data from early testing.…”

Section: Variabilitymentioning

confidence: 99%

“…Each of these has challenging implications for layout methodologies and design rules (DRs). Resolution enhancement techniques (RETs) and other patterning solutions such as immersion and doublepatterning technology (DPT), off-axis illumination (OAI), sub-resolution assist features (SRAFs), and phase-shift mask (PSM) require additional layout-restrictive DRs [5][6][7][8][9][10][11]. Therefore, early assessment of design restrictions imposed by technological choices is absolutely essential.…”

Section: Introductionmentioning

confidence: 99%

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DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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Section: Variabilitymentioning

confidence: 99%

Section: A Testing Setupmentioning

confidence: 99%