High performance CMOS current comparator using MTCMOS technique design

Saxena, Sachin; Akashe, Shyam

doi:10.1109/cipech.2014.7019090

Cited by 1 publication

(1 citation statement)

References 24 publications

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“…Sleep transistors, typically high-threshold PMOS or NMOS, are employed to cut power to specific sections of a device. MTCMOS devices are known for their reduced power consumption during idle states and lower latency [22,23]. The circuit was developed with possible changes in the size and quantity of HVT and LVT transistors along with a super cut-off mechanism.…”

Section: Methodsmentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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Section: Methodsmentioning

confidence: 99%