High performance CMOS fabricated on hybrid substrate with different crystal orientations

Abstract

A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on (110)-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2nm have been demonstrated, with substantial enhancement of pFET drive current at L,&8Gnm. IntroductionIt is known that hole mobility is more than doubled on (110) silicon substrates with current flow direction along <1 lo> [I -31 compared with conventional (1 00) substrates. However electron mobility is the highest on (100) substrates (Fig. I). To fully utilize the advantage of the carrier mobility dependence on surface orientation, in the present work we have developed a new technology to fabricate CMOS on hybrid substrates with different crystal orientations, with nFETs on silicon of (100) surface orientation and pFETs on (1 IO) surface orientation. High performance CMOS devices using 90nm technology with physical gate oxide thickness as thin as 1.2nm have been demonstrated. Significant pFET enhancement has been achieved.

Embedding Device Solutions in Engineered Substrates

“…Hybrid orientation composite SOI (HOT) is fabricated by transferring a (110) Si layer onto a (100) handle wafer. A (100) film on a (110) is another variation of a hybrid substrate [19]. For 40nm long pMOSFETs fabricated on a (110) surface, a current drive increase of 45% is achieved, but in contrast, the n-MOSFET on the (110) plane is degraded by 35% [19,20].…”

“…A strong overgrowth is required to drive defects out of the active area with facet formation above the substrate plane. A final CMP steps planarizes the topography and a composite wafer with (110) and (100) regions embedded in the same surface is obtained [19]. The obvious drawback of this approach is that one of the devices is fabricated on bulk.…”

“…The first one is evolutionary and takes advantage of strain inducing CMOS processes which can be further amplified by combining them with a strained silicon substrate (sSOI) [8,9]. The alternative and probably complementary approach is the dual crystal orientation surface with (100) and (110) Si surfaces for the n and p-channels, respectively [7,10]. Beyond 32nm, a hybrid material surface with tensile Si and compressive Ge or SiGe for the n and p-channels, respectively, may be the path to further mobility increase [11,12].…”

“…A (100) film on a (110) is another variation of a hybrid substrate [19]. For 40nm long pMOSFETs fabricated on a (110) surface, a current drive increase of 45% is achieved, but in contrast, the n-MOSFET on the (110) plane is degraded by 35% [19,20]. To overcome the n-channel degradation, windows corresponding to the n channel regions are etched in the substrate through the buried oxide down to the (100) handle substrate.…”

Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET

“…Such adverse effects can be easily avoided by combining bulk technology on the same wafer. The previous approach to integrating SOI and bulk technologies required the use of selective epitaxial growth to compensate for the height difference (Yang et al, 2003), which significantly increases process complexity. In this SOTB structure, bulk CMOSFETs for highvoltage I/O operation, ESD protection, and analog circuits can be easily integrated by removing the thin SOI/BOX layers.…”