High Performance CMOS Variability in the 65nm Regime and Beyond

Nassif, Sani R.; Bernstein, K.; Frank, D.J.; Gattiker, A.; Haensch, Wilfried; Ji, B.L.; Nowak, E.; Pearson, D.J.; Rohrer, Norman J.

doi:10.1109/iedm.2007.4419002

Cited by 85 publications

(60 citation statements)

References 4 publications

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“…In advanced technology nodes, variations in process, voltage, temperature and aging (PVTA) significantly impact circuit functionality and performance [1,2]. To ensure correct operations under all possible variations, suitable amount of timing margins must be added to the circuits [3].…”

Section: Introductionmentioning

confidence: 99%

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

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Section: Introductionmentioning

confidence: 99%

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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“…It is instructive to compare the above-mentioned variability sources in graphene with those in silicon technology [42,43,46,[96][97][98][99]. Both Class I and II graphene variabilities are analogous to the random variations in silicon devices (i.e.…”

Section: Variability Sources In Graphenementioning

confidence: 99%

mentioning

confidence: 99%

“…limits the reliability and yield); addressing this issue requires optimization of both device and circuit designs [41][42][43][44][45][46][47]. Variability sources in the standard complementary metal-oxide-semiconductor (CMOS) process can be categorized according to their spatial characteristics, time-scales, physical/environmental origins and systematic/random components [42,43,46]. And the nature of variability is likely to change with the progress of innovative materials, fabrication methods and device structures in the targeted applications [46,[48][49][50][51][52]: some variability sources may diminish while others may emerge; some can be minimized via device engineering (e.g.…”

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confidence: 99%

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Variability Effects in Graphene: Challenges and Opportunities for Device Engineering and Applications

Zhang

Duan

et al. 2013

Proc. IEEE

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Abstract-Variability effects in graphene can result from the surrounding environment and the graphene material itself, which form a critical issue in examining the feasibility of graphene devices for large-scale production. From the reliability and yield perspective, these variabilities cause fluctuations in the device performance, which should be minimized via device engineering. From the metrology perspective, however, the variability effects can function as novel probing mechanisms, in which the 'signal fluctuations' can be useful for potential sensing applications. This paper presents an overview of the variability effects in graphene, with emphasis on their challenges and opportunities for device engineering and applications. The discussion can extend to other thin-film, nanowire and nanotube devices with similar variability issues, forming general interest in evaluating the promise of emerging technologies.

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“…The distribution of h(D) is a normal distribution with mean 0 and variance σ 2 h . According to [1], [7], [4] we assume a worst-case value of σ h /D nom = 9%.…”

Section: Background On Variability Aware Delay and Energy Models mentioning

confidence: 99%

Variability-aware robust design space exploration of chip multiprocessor architectures

Palermo¹,

Silvano²,

Zaccaria³

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we introduce response surface modeling techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. We then introduce a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches. 1 I. INTRODUCTION Process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90 nm CMOS technologies. Parametric yield, i.e., the percentage of dies that meet power and performance constraints, has become as important as power and performance optimization itself.Manufacturing process variability is mainly due to inter-die and intra-die variations. Inter and intra-die variations affect low level process parameters such as the channel gate length, the thickness of the oxide and the threshold voltage, which, in turn, affect the critical path delay and static and dynamic power consumption. Inter-die fluctuations affect uniformly every element on a die and consist of lot-to-lot and wafer-towafer variations such as processing temperatures, equipment properties, wafer polishing, wafer placement and the resist thickness. Conversely, intra-die parameter fluctuations consist of both random and systematic components and generate nonuniform electrical characteristics across the chip [1].In this scenario, we address the problem of variabilityaware design at system-level for chip multi-processors (CMP). More precisely, we tackle the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints.The main contribution of this paper is twofold:• We introduce a design space exploration (DSE) framework which is robust with respect to manufacturing process variations. The main goal is the optimization of the dispersion of the target system metrics and the maximization of the yield of the system with respect to the application-level constraints.• The exploration process is supported by response surface modeling (RSM) techniques for improving the overall estimation time to obtain the system-level metrics associated to each system configuration. The DSE framework is based on a set of state-of-the-art accurate performance, area and energy models of a CMP

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High Performance CMOS Variability in the 65nm Regime and Beyond

Cited by 85 publications

References 4 publications

Light-weight one-cycle timing error correction based on hardware software co-design

Light-weight one-cycle timing error correction based on hardware software co-design

Variability Effects in Graphene: Challenges and Opportunities for Device Engineering and Applications

Variability-aware robust design space exploration of chip multiprocessor architectures

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