High-performance computing VLSI system for bit-parallel exponentiation inGF(2^m)

Abstract

Finite or Galois fields are used in numerous applications like error correcting codes in digital communication, pseudorandom number generation and cryptography. These applications often require computing exponentiation in GFð2 m Þ which is a very computationally intensive operation. This article presents a high-performance computing method for performing exponentiation in GFð2 m Þ. The key contribution of this article is to extend the bit-parallel structure for multiplication and division where bits of operands are processed at the same time, each bit traveling over a different path in the circuits to perform exponentiation. In addition, we also simplify the structure of parallel modules and pipelining stages in the proposed bit-parallel structure for exponentiation by considering the properties of GFð2 m Þ and hardwiring many constant terms. The circuit architecture for the developed structure is shown for the example case of m ¼ 4, and compared with existing approaches with respect to latency, hardware cost, area, delay, throughput and power dissipation for m ¼ 4 to 512. The results show that the proposed system has a low latency, hardware costs, area, delay and power dissipation that do not increase rapidly with increasing m and a high throughput that does not decrease rapidly as m increases compared with existing approaches.