High-performance Current Mode Receiver Design for On-chip VLSI Interconnects

Agrawal, Yash; Chandel, Rajeevan; Dhiman, Rohit

doi:10.1007/978-81-322-2268-2_54

Cited by 8 publications

(7 citation statements)

References 9 publications

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“…It is often designed using CMOS gate which is equivalently represented by load capacitance (C L ) [10,[25][26][27]. In CMS scheme, low impedance termination is achieved by using specialized current mode receiver circuits [28,29,32]. It is equivalently modeled by parallel combination of load resistance (R L ) and C L [31,33,34].…”

Section: Electrical Modeling Of Swcnt Bundle Interconnectmentioning

confidence: 99%

“…The signaling schemes in interconnect play a seminal role in enhancing the system performance. The traditional VMS scheme has full rail-to-rail swing whereas remarkable CMS scheme has reduced voltage swing over the interconnects [28,29]. CMS scheme possesses peculiar properties as high speed [28,30], high bandwidth [28], superior signal integrity [31] and high immune to electrostatic discharge (ESD) induced damage of MOS transistors [29].…”

Section: Introductionmentioning

confidence: 99%

“…The traditional VMS scheme has full rail-to-rail swing whereas remarkable CMS scheme has reduced voltage swing over the interconnects [28,29]. CMS scheme possesses peculiar properties as high speed [28,30], high bandwidth [28], superior signal integrity [31] and high immune to electrostatic discharge (ESD) induced damage of MOS transistors [29]. The reduced voltage swing in CMS scheme is obtained by using specialized low input impedance current-mode receiver circuits [28,29,31,32].…”

Section: Introductionmentioning

confidence: 99%

“…CMS scheme possesses peculiar properties as high speed [28,30], high bandwidth [28], superior signal integrity [31] and high immune to electrostatic discharge (ESD) induced damage of MOS transistors [29]. The reduced voltage swing in CMS scheme is obtained by using specialized low input impedance current-mode receiver circuits [28,29,31,32]. Until now, nearly all of the researches were focused on voltage mode signaling (VMS) scheme for SWCNT bundle interconnect [10,[18][19][20][21][22][23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

“…Until now, nearly all of the researches were focused on voltage mode signaling (VMS) scheme for SWCNT bundle interconnect [10,[18][19][20][21][22][23][24][25][26][27]. In [28,[31][32][33][34], the performance of copper interconnect using CMS scheme has been explored. It is investigated that CMS copper interconnect possesses high speed and bandwidth as compared to VMS copper interconnect.…”

Section: Introductionmentioning

confidence: 99%

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An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect

Agrawal

Girish²,

Chandel

2018

Sādhanā

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Carbon nanotube (CNT) has emerged as the most extensively researched area in nanoscience and amongst the frontrunners in co-triggering the nanotechnology revolution. Single-wall CNT (SWCNT) bundle is a part of CNT family and has been proposed as the future nano-wires in integrated circuits. The present paper analyzes the performance of SWCNT bundle interconnect with high-speed current-mode signaling (CMS) scheme using efficient finite-difference time-domain (FDTD) method. For the first time, FDTD based method is explored for modeling CMS SWCNT bundle interconnect incorporating practical CMOS driver gate. The CMOS gate is characterized by n th power-law model. The stability of FDTD method is ascertained by Courant condition. The proposed FDTD based method is efficient and can be used for performance analyses of future nano-wire SWCNT bundle as well as conventional copper interconnects. At the same time, this method is applicable for both traditional full-voltage swing voltage-mode signaling (VMS) and remarkable low-voltage swing CMS schemes. The various analyses in the paper reveal that CMS SWCNT bundle interconnect has higher edge over CMS copper interconnect in terms of smaller delay, lesser crosstalk induced delay and noise. The proposed analytical FDTD based method is validated using Tanner-SPICE EDA simulation tool. The maximum error between the FDTD and SPICE for the transient response in CMS SWCNT bundle interconnect for 32 nm technology node is within 3%. Keywords. Current-mode signaling (CMS); finite-difference time-domain (FDTD); nanotechnology; on-chip interconnect; single-wall carbon nanotube (SWCNT) bundle.

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Section: Electrical Modeling Of Swcnt Bundle Interconnectmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect

Agrawal

Girish²,

Chandel

2018

Sādhanā

Self Cite

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Optimized buffer insertion for efficient interconnects designs

Khursheed

Khare

2020

Int J Numerical Modelling

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This typescript focuses on unraveling the functional performance deterioration issues related to conventional Cu on‐chip nanointerconnecting wires; mainly occurred due to the shrinking of device dimensions. Buffer insertion methodology proves to be an effective approach for designing high‐speed interconnect network but at the cost of power consumption. Moreover, ramification of too many buffers as repeaters leads to area overhead. Hence an optimized number must be judicially decided. Proposed circuits for buffers are modeled using variable diameter and multi Vt design techniques to balance delay as well as average power consumption. Interconnects designed with conventional Cu interconnect technology are compared with state of art CNT technology at different lengths. Proposed and Existing Buffer circuit architectures are modeled with both CNT and MOS technology to carry out the comparative simulation analysis using varied combination of CNTFET buffer‐CNT interconnect and CMOSFET buffer‐Cu interconnect. Benchmarking with conventional buffer circuits, simulated results illustrates that ProposedBuffer1 saves dynamic power by 89.96%, leakage power by 89%, and offers delay mitigation by 77.5%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 97.53%, but causes delay penalty. All the HSPICE simulations are carried out using Stanford SPICE model for CNT and BSIM4 PTM for MOS at 32 nm.

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