High performance DMA controller for ultra HDTV video codecs

Nandan, Niraj

doi:10.1109/icce.2014.6775910

Cited by 6 publications

(3 citation statements)

References 1 publication

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“…This fact is exploited to create a hierarchical caching scheme where multiple levels of comparisons are done to reduce the comparison cost. This is described in detail in [4] and [5]. In case of Ultra-HD content, horizontal caching is not sufficient to exploit overlap in reference data fetches in the vertical direction as it maintains small history.…”

Section: Optimizing External Sdram Accesses In Decodermentioning

confidence: 98%

“…It contains different hardware accelerators (HWA) for motion estimation (ME), spatial intra prediction (IPE), Transform and Quantization Engine (CALC), Motion compensation (MC [2]), De-blocking filter (LPF [3]) and Entropy codec (ECD). It also has a Video DMA Engine (VDMA) optimized for 2D block-transfers required in video processing [4]. The overall data flow control and interaction with the external CPU host is managed by two specialized Video RISC Processors (ICONT1/2).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A monolithic programmable Ultra-HD video codec engine

Sanghvi

Mody

Nandan

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Self Cite

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With advances in video coding standards like H.264 and HEVC coupled with those in the display technology, Ultra HD contents have started taking the mainstream. This is driving the need for high computation and memory bandwidth in current multi-media SOCs. In this paper, we present a monolithic multi-format video codec engine which achieves Ultra HD performance for H.264 High Profile, reduces the external memory bandwidth requirement by 2X as compared to its predecessor and takes only 5.9 mm 2 of silicon area in a low power 28nm process.

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Section: Optimizing External Sdram Accesses In Decodermentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

A monolithic programmable Ultra-HD video codec engine

Sanghvi

Mody

Nandan

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Self Cite

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show abstract

“…DMA engine with frequency of 266 MHz, which provides the 4K processing per 16×16 within 200 cycles, is discussed for the video codecs. The proposed DMA has less 4 nw power and showing less efficient in area [7]. Ahmed et al [8] proposed the DMA based controller for multiple embedded systems.…”

Section: Introductionmentioning

confidence: 99%

Improving graphics processing unit performance based on neural network direct memory access controller

Kumar,

Neelappa,

Bhusare

et al. 2023

IJEECS

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In this paper proposes the design and implementation of the back propagation algorithm based neural network DMA (Direct Memory Access) Controller for use of multimedia applications. The proposed DMA controller work with the back propagation-training algorithm. The advantages of the back propagation algorithm it will be work on the gradient loss w.r.t the network weights. So this back propagation algorithm is used as training algorithm for the DMA controller. The proposed method is test with the different workload characteristics like heavy workload, medium workload and normal workload. The performance parameters are considered here is like accuracy, precision, recall and F1 score etc. The proposed method is compared with existing methods like CNN (Convolutional Neural Network), RNN (Recurrent Neural Network), LSTM (Long Sort term Memory) and GRU (Gated Recurrent Unit) etc. Finally, the proposed design will give the better performance than existing methods.

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Design and implementation of a flexible DMA controller in video codec system

Wang

Zhou

et al. 2014

2014 19th International Conference on Digital Signal Processing

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High performance DMA controller for ultra HDTV video codecs

Cited by 6 publications

References 1 publication

A monolithic programmable Ultra-HD video codec engine

A monolithic programmable Ultra-HD video codec engine

Improving graphics processing unit performance based on neural network direct memory access controller

Design and implementation of a flexible DMA controller in video codec system

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