High performance FDSOI CMOS technology with metal gate and high-k

Abstract

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Workfunction tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T inv ) down to 14Å with a gate leakage current of 0.2A/cm 2 . This represents a six order of magnitude leakage reduction compared to Poly/SiO 2 . By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm 2 /Vs at E eff =1MV/cm) at T inv =14Å. Drive currents of 1050µA/µm and 770µA/µm at I off of 90nA/µm and 28nA/µm are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V dd =1.2V.Introduction Gate dielectric scaling has been a key component of each technology generation for over thirty years. Unfortunately, extremely thin state-of-the-art SiON based oxides can no longer be scaled due to excessive gate leakage. High-k gate dielectrics offer the possibility of continued T inv scaling with the added benefit of gate leakage reduction. However, mobility degradation, Fermi level pinning, and V t instability have prevented insertion of high-k dielectrics into mainstream manufacturing. Recent results suggest that combining metal gates along with high-k dielectrics minimizes mobility degradation and Fermilevel pinning [1][2][3]. An additional barrier to realizing metal gate/high-k technology is that bulk and PDSOI CMOS require band edge work function metals to achieve appropriate threshold voltages. To be compatible with conventional gate first process flows these materials must also be thermally stable to high temperatures.Undoped FDSOI has significant advantages compared to bulk and PDSOI. Charge carrier mobility is higher since FDSOI operates at lower vertical field and Coulomb scattering is negligible. In addition, the random dopant fluctuations associated with halo implants are eliminated. The sub-threshold swing is steeper for FDSOI as a result of the strong gate to channel coupling. Short channel effects in FDSOI devices are controlled by the thin SOI channel rather than high dose halo implants as is the case for bulk and PDSOI. This allows the requirement for FDSOI metal gate work functions to be relaxed from band edge to somewhere between mid-gap and band edge [4]. Thus, high-k/metal gate stacks are an attractive option for FDSOI technology and will enable the gate dielectric scaling trend to continue. In this work we evaluate gate stacks for FDSOI technology and present high performance devices and circuits. Experiment The FDSOI channels were thinned to 140Å +/-20Å by oxidizing and wet etching bonded SOI wafers. Devices are isolated by a shallow trench scheme. Several different gate materials and processes were evaluated (Table 1). Interfacial layers were forme...

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