High Performance FPGA-Based DMA Interface for PCIe

Kavianipour, Hossein; Muschter, Steffen; Böhm, C.

doi:10.1109/tns.2014.2304691

Cited by 42 publications

(17 citation statements)

References 5 publications

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“…Packets should be serially assembled and transaction of packets is occurred in different three layers: Transaction layer, Data Link layer, Physical layer [3] . After passing these three layers, data is interchange among the devices.…”

Section: Pcie Stackmentioning

confidence: 99%

See 1 more Smart Citation

PCIe BUS: A State-of-the-Art-Review

Verma¹,

Dahiya²

2017

IOSR JVSP

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Section: Pcie Stackmentioning

confidence: 99%

“…It is the improved version of PCI-X (Extended). PCIe is usually deployed with different 1, 4, 8, 12, 16 or 32 lanes for the implementation to the motherboard [3].…”

Section: Introductionmentioning

confidence: 99%

PCIe BUS: A State-of-the-Art-Review

Verma¹,

Dahiya²

2017

IOSR JVSP

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“…3 Driver is closed source, thus analysis is not possible. DyRACT [10], EPEE [11], FlexWAFE [12], Speedy [13] as well as the implementation of Kavianipour et al [14], are PCIe solutions supporting generation 2. Kavianipour is slow, peaking at 52 % of the theoretical bandwidth.…”

Section: Available Pcie Solutionsmentioning

confidence: 99%

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

Vesper

Koch

Vipin

et al. 2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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“…The circuit is divided into PCIe [6,7] module, TOE module, Encryption module, Ethernet MAC. TOE module, PCIe module and Ethernet MAC are implemented by IP core on the FPGA.…”

Section: The Design Of the Encryption Systemmentioning

confidence: 99%

Application and Implementation of DES Algorithm Based on FPGA

Zhao¹

2016

Proceedings of the 2016 4th International Conference on Management, Education, Information and Control (MEICI 2016)

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Abstract. In order to meet the data transmission of security and real time requirement in trading system, in this paper, a design scheme of 16 level pipeline encryption system based on FPGA is proposed. Using the 7K325T model of the Xilinx company`s FPGA chip to achieve circuit design. The results show that the circuit can work stably, the maximum frequency of the encryption module is up to 166MHz, and the encryption speed is 10.62Gb/s, which can ensure the security and efficiency of the data.

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High Performance FPGA-Based DMA Interface for PCIe

Cited by 42 publications

References 5 publications

PCIe BUS: A State-of-the-Art-Review

PCIe BUS: A State-of-the-Art-Review

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

Application and Implementation of DES Algorithm Based on FPGA

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