High performance full adder cell: A comparative analysis

Sharma, Tripti; Sharma, K. G.; Singh, B. P.

doi:10.1109/techsym.2010.5469170

Cited by 14 publications

(4 citation statements)

References 6 publications

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“…Fig. 10 shows the block diagram and simulation result for half adder and full adder by using NAND and XOR logic we mentioned above [27,28,29]. From the simulation result in Fig.…”

Section: Fundamental Circuitsmentioning

confidence: 99%

Non-floating and low-power adiabatic logic circuit

Han

Takahashi

Sekine

2019

IEICE Electron. Express

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This paper proposes a new adiabatic logic. Adiabatic logic is a good method to reduce power consumption. Several common adiabatic logics suffer from floating output which results in lack in robustness, by using the periodic power supply. At first, we analyze the floating phenomenon of previously proposed 2PC2AL in this paper. The proposed adiabatic logic can prevent the floating of the nodes to add two logic switches between the power supply and charging-discharging transistor. This paper also reports a comparison of energy dissipation between the different adiabatic logics such as, ECRL, 2N2N2P, 2PASCL, 2PC2AL, and the proposed circuit. In the SPICE simulation, the target application is a 4-bit multiplier for IoT products. Through the simulation, the output of the proposed circuit with cascade connection has a stable function.

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“…Fig. 10 shows the block diagram and simulation result for half adder and full adder by using NAND and XOR logic we mentioned above [27,28,29]. From the simulation result in Fig.…”

Section: Fundamental Circuitsmentioning

confidence: 99%

Non-floating and low-power adiabatic logic circuit

Han

Takahashi

Sekine

2019

IEICE Electron. Express

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“…In order to reduce the power consumption and area in CLA, the single‐bit full adder has to be improved to increase the performance. Various techniques for developing the improved structure of XOR gate and single‐bit full adder have been proposed in the previous research work. Full adder utilizes XOR gate to implement the addition operation in the digital circuits.…”

Section: Implementation Of 10 T Full Addermentioning

confidence: 99%

High performance 8 bit cascaded carry look ahead adder with precise power consumption

Johri

Akashe

Sharma

2014

Int J Communication

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SUMMARYMultiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be replaced with fast adders as carry-look-ahead adder (CLA). Power consumption in digital circuits depends on the number of metal-oxide-semiconductor field-effect transistor employed and various other parameters. If number of metal-oxide-semiconductor field-effect transistor is reduced the power consumption would definitely be reduced. Conventional CLAs would consume significant amount of power that still needs to be improved. The paper here deals with the implementation of 8 bit CLA with the aim of reducing the size and to precise the power consumption within nanowatt range, by improving the fundamental components of the circuit. All the parameters have been calculated by using Cadence Virtuoso tool at 45 nm technology.

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“…Research conducted in [19] analyzed the performance of FA in treestructured arithmetic units. In [20], only 4 FA cells have been analyzed and compared. However, these studies are not up-to-date as they do not have the FA designs developed in the past 10 years.…”

Section: Introductionmentioning

confidence: 99%

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

et al. 2021

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Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness.

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High performance full adder cell: A comparative analysis

Cited by 14 publications

References 6 publications

Non-floating and low-power adiabatic logic circuit

Non-floating and low-power adiabatic logic circuit

High performance 8 bit cascaded carry look ahead adder with precise power consumption

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

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