High performance fully-depleted tri-gate CMOS transistors

Doyle, B.S.; Datta, Suman; Doczy, M.; Hareland, S.A.; Jin, B.; Kavalieros, J.; Linton, T.; Murthy, A.; Rios, R.; Chau, R.

doi:10.1109/led.2003.810888

Cited by 433 publications

(201 citation statements)

References 10 publications

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“…The observation of similar dot widths of a few nanometers for different fin widths of hundreds of nanometers is consistent with the idea of a dot located at the edge of the fin and thus with the corner effect. 3,4 In addition to a large charging energy E c = ␣e⌬V G , these dots also have a large quantum level spacing ⌬E, as can be deduced from the temperature dependence of the conductance peaks in Fig. 3͑c͒.…”

Section: -mentioning

confidence: 91%

“…These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50ϫ 60ϫ 35 nm 3 . Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate.…”

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confidence: 99%

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Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Sellier

Lansbergen

Caro

et al. 2007

Applied Physics Letters

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The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50ϫ 60ϫ 35 nm 3 . Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2476343͔ Nonplanar field-effect transistors called FinFETs ͑Ref. 1͒ are currently being developed to solve the problematic issues encountered with the standard planar geometry when the channel length is reduced to a sub-100 nm size. Their triplegate geometry is expected to have a more efficient gate action and to solve the leakage problem through the body of the transistor, one of the dramatic short channel effects. 2 However, their truly three-dimensional ͑3D͒ structure makes doping-and thus also potential-profiles very difficult to simulate and to understand using the current knowledge on device technology. Transport studies at low temperature, where the thermally activated transport is suppressed, can bring insight to these questions by measuring local gate action. For this reason we experimentally investigate the potential profile by conductance measurements and observe the formation of a subthreshold channel at the edge of the silicon nanowire. This corner effect has been proposed 3,4 as an additional contribution to the subthreshold current in these 3D triple-gate structures, where the edges of the nanowire experience stronger gate action due to the geometric enhancement of the field. However, besides extensive simulation work 3,4 -keeping in mind the difficulties with these 3D structures-very little experimental work has been published until now on this effect. 5 The FinFETs discussed here consist of a narrow singlecrystalline silicon wire with two large contact pads etched in a p-type silicon on insulator layer doped with 10 18 cm −3 boron atoms. This silicon wire is covered with a t ox = 1.4 nm thick thermal oxide and a second narrow polycrystalline silicon wire crossing the first one is fabricated to form a gate that surrounds the wire on three faces ͓Fig. 1͑a͔͒. The entire surface is then implanted with 10 19 cm −3 arsenic atoms to form n-type degenerate source, drain, and gate. During this implantation the wire located below the gate is protected and remains p type. In the investigated device series the height of the fin wire is H = 60 nm, while the width ranges from W =35 nm to 1 m and the gate length ranges from L =50 nm to 1 m. The relatively high p-type doping of the channel wire is chosen to ensure a depletion...

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Section: -mentioning

confidence: 91%

mentioning

confidence: 99%

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Sellier

Lansbergen

Caro

et al. 2007

Applied Physics Letters

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“…Significant attempts have been highlighted in the literature (Langmuir Blodgett [205], dielectrophoresis [206], fluidic alignment [207]) to align nanowires but these techniques never match the nanometre tolerances required for precision placement and overlay within semiconductor high volume manufacturing. Apart from the obvious benefits of using semiconductor nanowires in microelectronic devises, such as resolution enhancement and density, other advantages include the ability to generate cross-bar arrays of nanowires [208], reduced power consumption and increased electrostatic control through the use of a wrap-around gate dielectrics [209].…”

Section: Nanowire Arraysmentioning

confidence: 99%

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Farrell

Petkov²,

Morris

et al. 2010

Journal of Colloid and Interface Science

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Self-assembled nanoscale porous architectures, such as mesoporous silica films (MPS), block copolymer films (BCP) and porous anodic aluminas (PAAs), are ideal hosts for templating one dimension (1 D) nano-entities for a wide range of electronic, photonic, magnetic and environmental applications. All three templates offer dimensional scalability and tunability over a wide range, with critical pore sizes for each system well below the 20 nm threshold [1][2][3]. Recently, research has progressed towards controlling the pore direction, orientation and long range order of these nanostructures through so called directed self-assembly (DSA). Significantly, the introduction of a wide range of top-down chemically and physically pre-patterning substrates has facilitated the DSA of nanostructures into functional device arrays. The following review begins with an overview of the fundamental aspects of self-assembly and ordering processes during the formation of PAAs, BCPs and MPS films. Special attention is given to the different ways of directing self-assembly, concentrating on properties such as uni-directional alignment, precision placement and registry of the self-assembled structures to hierarchal or top down architectures. Finally, to distinguish this review from other articles we focus on research where nanostructures have been utilised in part to fabricate arrays of functioning devices below the sub 50 nm threshold, by subtractive transfer and additive methods. Where possible, we attempt to compare and contrast the different templating approaches and highlight the strengths and/or limitations that will be important for their potential integration into downstream processes. ACCEPTED MANUSCRIPT 3 SECTION 1.0: SELF ASSEMBLY AND NANO-ARCHITETCURESThe diversity of self-assembled nanostructures and more importantly, their precise orientation within a thin film (fixed to a substrate) ultimately determines their function and overall application. A large population of research reports to date have focused on identifying these orientations and related periodicities, using x-ray and microscopy tools, as well the development of methods for readily manipulating nanostructures, such as pre-patterning of silicon substrates for the alignment of block copolymers (BCPs) [4] and mesoporous thin films (MTFs) [5] and altering the growth direction of porous anodic alumina (PAA) templates [6]. In this section, a brief synopsis of the mechanisms behind the self-assembly/organisation of each system and highlight nanoscale architectures (and orientations), which are important from a device perspective. Templated mesoporous thin filmsOrdered mesoporous powders were first discovered by researchers at the Mobil Petrochemical Corporation in 1992 and shortly after, sol-gel derived mesoporous silica films were fabricated [1,7].The first series of ordered mesoporous films were reported by Yang et al. in 1996 [8], prepared using initial surfactant concentrations above their critical micelle concentration (CMC). However the films prepared fil...

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“…The research can be categorized as -research on alternative gate dielectrics like hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ) and titanium dioxide (TiO 2 ) and alternative device geometries like Double Gate MOSFET (DGMOSFET), tri-gate, gate all around) structures, silicon nanowire transistors (SNWT) etc. Effective gate control can be achieved by the multigate structures [4]- [6]. Another effective device structure was proposed in [8]- [9] which involves replacing the gate oxide of the MOSFET with a RTD (resonant tunneling diode) based structure.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of MISISFET- TCAD Simulation

Chaudhary¹,

Khanna²,

Chandel³

2012

IJCA

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A novel device n-MISISFET with a "dielectric stack" instead of the single insulator of n-MOSFET has been described and its characteristics has been obtained in this paper. The desired variation of threshold voltage is obtained with biasing for the novel n-MISISFET for various substrate doping concentrations, the effect temperature variation on various electrical characteristics is studied in the paper. The variation of electric field with substrate doping is also studied in this paper. The device is based on the principle of resonant tunneling diode (RTD).

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High performance fully-depleted tri-gate CMOS transistors

Cited by 433 publications

References 10 publications

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Performance Evaluation of MISISFET- TCAD Simulation

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